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Optimization and Modeling of npn-Type Selector for Resistive RRAM in Cross-Point Array Structure
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 조성재 | - |
| dc.date.available | 2020-04-24T07:40:25Z | - |
| dc.date.issued | 2014-06-09 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/29055 | - |
| dc.title | Optimization and Modeling of npn-Type Selector for Resistive RRAM in Cross-Point Array Structure | - |
| dc.type | Conference | - |
| dc.citation.conferenceName | 2014 IEEE Silicon Nanoelectronics Workshop (SNW) | - |
| dc.citation.conferencePlace | 미국 | - |
| dc.citation.conferencePlace | Honolulu, USA | - |
| dc.citation.endPage | 177 | - |
| dc.citation.startPage | 176 | - |
| dc.citation.title | Proceedings of 2014 IEEE SNW | - |
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Related Researcher
- Cho, Seong Jae
- IT (Major of Electronic Engineering)