Simulation of One-Transistor Dynamic Random-Access Memory Based on Symmetric Double-Gate Si Junctionless Transistor
DC Field | Value | Language |
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dc.contributor.author | Kim, Bo Gyeong | - |
dc.contributor.author | Seo, Jae Hwa | - |
dc.contributor.author | Yoon, Young Jun | - |
dc.contributor.author | Cho, Min Su | - |
dc.contributor.author | Yu, Eunseon | - |
dc.contributor.author | Lee, Jung-Hee | - |
dc.contributor.author | Cho, Seongjae | - |
dc.contributor.author | Kang, In Man | - |
dc.date.available | 2020-02-27T09:41:36Z | - |
dc.date.created | 2020-02-07 | - |
dc.date.issued | 2018-09 | - |
dc.identifier.issn | 1533-4880 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/3352 | - |
dc.description.abstract | In this study, one-transistor dynamic random-access memory (1T-DRAM) based on a symmetric double-gate Si junctionless transistor is proposed using technology computer-aided design simulation. The proposed device uses double gates that play different roles in realizing 1T-DRAM operation. Gate 1 is used as a switching node, and Gate 2 is used as a storage node. By controlling the different two gate workfunctions, a potential barrier is adjusted to store hole effectively. The operation characteristics were investigated regarding four different memory operation states to write "1", write "0", read, and hold. Also, the effects of two different gate workfunctions on sensing margin and retention characteristics are closely investigated. Through a set of optimally set gate workfunctions, 33 mu A/mu m of sensing margin and 38 ms of retention time have been obtained. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | AMER SCIENTIFIC PUBLISHERS | - |
dc.relation.isPartOf | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY | - |
dc.subject | CAPACITORLESS 1T-DRAM | - |
dc.subject | DRAM CELL | - |
dc.subject | SOI | - |
dc.subject | OPERATION | - |
dc.subject | MOSFETS | - |
dc.title | Simulation of One-Transistor Dynamic Random-Access Memory Based on Symmetric Double-Gate Si Junctionless Transistor | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000430706900135 | - |
dc.identifier.doi | 10.1166/jnn.2018.15707 | - |
dc.identifier.bibliographicCitation | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v.18, no.9, pp.6593 - 6597 | - |
dc.citation.endPage | 6597 | - |
dc.citation.startPage | 6593 | - |
dc.citation.title | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY | - |
dc.citation.volume | 18 | - |
dc.citation.number | 9 | - |
dc.contributor.affiliatedAuthor | Yu, Eunseon | - |
dc.contributor.affiliatedAuthor | Cho, Seongjae | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | 1T-DRAM | - |
dc.subject.keywordAuthor | Double-Gate Junctionless Field-Effect Transistor | - |
dc.subject.keywordAuthor | TCAD Simulation | - |
dc.subject.keywordAuthor | Gate Workfunction | - |
dc.subject.keywordPlus | CAPACITORLESS 1T-DRAM | - |
dc.subject.keywordPlus | DRAM CELL | - |
dc.subject.keywordPlus | SOI | - |
dc.subject.keywordPlus | OPERATION | - |
dc.subject.keywordPlus | MOSFETS | - |
dc.relation.journalResearchArea | Chemistry | - |
dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Chemistry, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Nanoscience & Nanotechnology | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.relation.journalWebOfScienceCategory | Physics, Condensed Matter | - |
dc.description.journalRegisteredClass | scie | - |
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