Characterization and Optimization of Inverted-T FinFET Under Nanoscale Dimensions
DC Field | Value | Language |
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dc.contributor.author | Yu, Eunseon | - |
dc.contributor.author | Heo, Keun | - |
dc.contributor.author | Cho, Seongjae | - |
dc.date.available | 2020-02-27T09:42:39Z | - |
dc.date.created | 2020-02-07 | - |
dc.date.issued | 2018-08 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/3496 | - |
dc.description.abstract | In this paper, a p-type inverted-T FinFET (IT FinFET) has been optimally structured. Focus is made on analyzing the inferior characteristics reported from the previously fabricated IT FinFETs, and obtaining better performances through a novel structure. IT FinFET has a higher layout efficiency and can thus provide larger drain current (I-D) under the same dimension as that of a silicon-oninsulator (SOI) FinFET by securing the extended channels of ultrathin body (UTB) on the field region. We closely observe the leverages of fin width (W-fin), UTB height (H-UTB), and gate length (L-g) on the operation characteristics using a 3-D technology computer-aided design simulation with quantum-mechanicalmodels. Wfin below 10 nmis evaluated to be suitable for strong gate controllability. We first examine a critical H-UTB, beyond which a higher drive current is not obtained even with a greater channel width than that of FinFET. When H-UTB = 3 and 10 nm, IT FinFET yields 13.3% and 142% of saturation current improvement compared with SOI FinFET under the same footprint. At extremely scaled Lg, although the immunity against short-channel effects is slightly weaker than that of SOI FinFET, optimally designed IT FinFET can produce a higher current and demonstrates shorter intrinsic delay times. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.subject | SI | - |
dc.subject | MOBILITY | - |
dc.subject | DESIGN | - |
dc.subject | MODEL | - |
dc.subject | CMOS | - |
dc.subject | HFO2 | - |
dc.subject | GE | - |
dc.title | Characterization and Optimization of Inverted-T FinFET Under Nanoscale Dimensions | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000439649900063 | - |
dc.identifier.doi | 10.1109/TED.2018.2846478 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.65, no.8, pp.3521 - 3527 | - |
dc.identifier.scopusid | 2-s2.0-85049132980 | - |
dc.citation.endPage | 3527 | - |
dc.citation.startPage | 3521 | - |
dc.citation.title | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.citation.volume | 65 | - |
dc.citation.number | 8 | - |
dc.contributor.affiliatedAuthor | Yu, Eunseon | - |
dc.contributor.affiliatedAuthor | Cho, Seongjae | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | 3-D technology computer-aided design (TCAD) simulation | - |
dc.subject.keywordAuthor | high current drive | - |
dc.subject.keywordAuthor | high performance (HP) | - |
dc.subject.keywordAuthor | intrinsic gate delay | - |
dc.subject.keywordAuthor | inverted-T FinFET (IT FinFET) | - |
dc.subject.keywordAuthor | low power operation | - |
dc.subject.keywordAuthor | short-channel effects (SCEs) | - |
dc.subject.keywordAuthor | silicon-on-insulator (SOI) FinFET | - |
dc.subject.keywordAuthor | wavy FinFET | - |
dc.subject.keywordPlus | SI | - |
dc.subject.keywordPlus | MOBILITY | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | MODEL | - |
dc.subject.keywordPlus | CMOS | - |
dc.subject.keywordPlus | HFO2 | - |
dc.subject.keywordPlus | GE | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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