Investigation of Modified 1T DRAM with Twin Gate Tunneling Field Effect Transistor for Improved Retention Characteristics
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Dong Chang Han | - |
dc.contributor.author | Deok Jin Jang | - |
dc.contributor.author | Jae Yoon Lee | - |
dc.contributor.author | Seongjae Cho | - |
dc.contributor.author | Il Hwan Cho | - |
dc.date.available | 2020-05-18T09:35:57Z | - |
dc.date.created | 2020-05-06 | - |
dc.date.issued | 2020-04 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/43542 | - |
dc.description.abstract | This paper proposes a one transistor dynamic random access memory (1T DRAM) with localized partial insulator (LPI) to increase data retention time. Proposed 1T DRAM cell is based on twin gate tunneling field effect transistor (TGTFET) and has improved retention characteristics with LPI. The LPI inhibit stored carrier movement with high energy barrier. Key process sequence is suggested and device optimizations with parameter variation are also investigated with device simulation. As the barrier length increases, retention characteristics can be improved but also it causes a decrease in the read 1 current. An increase in LPI length within the appropriate range is required in the proposed 1T DRAM. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | 대한전자공학회 | - |
dc.relation.isPartOf | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.title | Investigation of Modified 1T DRAM with Twin Gate Tunneling Field Effect Transistor for Improved Retention Characteristics | - |
dc.title.alternative | Investigation of Modified 1T DRAM with Twin Gate Tunneling Field Effect Transistor for Improved Retention Characteristics | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000530108200003 | - |
dc.identifier.doi | 10.5573/JSTS.2020.20.2.145 | - |
dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.20, no.2, pp.145 - 150 | - |
dc.identifier.kciid | ART002580894 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.scopusid | 2-s2.0-85084109542 | - |
dc.citation.endPage | 150 | - |
dc.citation.startPage | 145 | - |
dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.volume | 20 | - |
dc.citation.number | 2 | - |
dc.contributor.affiliatedAuthor | Jae Yoon Lee | - |
dc.contributor.affiliatedAuthor | Seongjae Cho | - |
dc.subject.keywordAuthor | 1T DRAM | - |
dc.subject.keywordAuthor | tunnel FET (TFET) | - |
dc.subject.keywordAuthor | localized partial insulator (LPI) | - |
dc.subject.keywordAuthor | reliability | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
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