Effects of nitride trap layer properties on location of charge centroid in charge-trap flash memory
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, S. | - |
dc.contributor.author | Kim, D.-B. | - |
dc.contributor.author | Yu, E. | - |
dc.contributor.author | Lee, S.-H. | - |
dc.contributor.author | Cho, S. | - |
dc.contributor.author | Park, B.-G. | - |
dc.date.available | 2020-02-27T20:43:06Z | - |
dc.date.created | 2020-02-12 | - |
dc.date.issued | 2017 | - |
dc.identifier.issn | 0000-0000 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/6706 | - |
dc.description.abstract | In this study, the effects of nitride trap layer properties on location of charge centroid in charge-trap flash (CTF) memory are closely investigated. In the operations of CTF memories, charges tunnel into the nitride layer through thin oxide, unlike the floating-gate (FG) type flash memory where the charges are stored in the conductive poly-crystalline Si. Deeper understanding of distribution of the trapped charges should be beneficial in setting up an accurate compact model of CTF memory cell, where the charge centroid becomes a very practical means by which a rather large number of trapped electrons can be dealt in the more mathematical manner as a whole electron cloud. The relation between charge centroid and program voltage (VPGM) depending on nitride layer properties is analytically studied. © 2017 JSAP. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.relation.isPartOf | 2017 Silicon Nanoelectronics Workshop, SNW 2017 | - |
dc.subject | Charge trapping | - |
dc.subject | Nanoelectronics | - |
dc.subject | Nitrides | - |
dc.subject | Charge centroid | - |
dc.subject | Charge trap flash memory | - |
dc.subject | Electron clouds | - |
dc.subject | Floating gates | - |
dc.subject | Polycrystalline | - |
dc.subject | Program voltage | - |
dc.subject | Trapped charge | - |
dc.subject | Trapped electrons | - |
dc.subject | Flash memory | - |
dc.title | Effects of nitride trap layer properties on location of charge centroid in charge-trap flash memory | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.doi | 10.23919/SNW.2017.8242306 | - |
dc.identifier.bibliographicCitation | 2017 Silicon Nanoelectronics Workshop, SNW 2017, v.2017-January, pp.79 - 80 | - |
dc.identifier.scopusid | 2-s2.0-85051001839 | - |
dc.citation.endPage | 80 | - |
dc.citation.startPage | 79 | - |
dc.citation.title | 2017 Silicon Nanoelectronics Workshop, SNW 2017 | - |
dc.citation.volume | 2017-January | - |
dc.contributor.affiliatedAuthor | Yu, E. | - |
dc.contributor.affiliatedAuthor | Cho, S. | - |
dc.type.docType | Conference Paper | - |
dc.subject.keywordPlus | Charge trapping | - |
dc.subject.keywordPlus | Nanoelectronics | - |
dc.subject.keywordPlus | Nitrides | - |
dc.subject.keywordPlus | Charge centroid | - |
dc.subject.keywordPlus | Charge trap flash memory | - |
dc.subject.keywordPlus | Electron clouds | - |
dc.subject.keywordPlus | Floating gates | - |
dc.subject.keywordPlus | Polycrystalline | - |
dc.subject.keywordPlus | Program voltage | - |
dc.subject.keywordPlus | Trapped charge | - |
dc.subject.keywordPlus | Trapped electrons | - |
dc.subject.keywordPlus | Flash memory | - |
dc.description.journalRegisteredClass | scopus | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
1342, Seongnam-daero, Sujeong-gu, Seongnam-si, Gyeonggi-do, Republic of Korea(13120)031-750-5114
COPYRIGHT 2020 Gachon University All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.