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Effects of nitride trap layer properties on location of charge centroid in charge-trap flash memory

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dc.contributor.authorKim, S.-
dc.contributor.authorKim, D.-B.-
dc.contributor.authorYu, E.-
dc.contributor.authorLee, S.-H.-
dc.contributor.authorCho, S.-
dc.contributor.authorPark, B.-G.-
dc.date.available2020-02-27T20:43:06Z-
dc.date.created2020-02-12-
dc.date.issued2017-
dc.identifier.issn0000-0000-
dc.identifier.urihttps://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/6706-
dc.description.abstractIn this study, the effects of nitride trap layer properties on location of charge centroid in charge-trap flash (CTF) memory are closely investigated. In the operations of CTF memories, charges tunnel into the nitride layer through thin oxide, unlike the floating-gate (FG) type flash memory where the charges are stored in the conductive poly-crystalline Si. Deeper understanding of distribution of the trapped charges should be beneficial in setting up an accurate compact model of CTF memory cell, where the charge centroid becomes a very practical means by which a rather large number of trapped electrons can be dealt in the more mathematical manner as a whole electron cloud. The relation between charge centroid and program voltage (VPGM) depending on nitride layer properties is analytically studied. © 2017 JSAP.-
dc.language영어-
dc.language.isoen-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.relation.isPartOf2017 Silicon Nanoelectronics Workshop, SNW 2017-
dc.subjectCharge trapping-
dc.subjectNanoelectronics-
dc.subjectNitrides-
dc.subjectCharge centroid-
dc.subjectCharge trap flash memory-
dc.subjectElectron clouds-
dc.subjectFloating gates-
dc.subjectPolycrystalline-
dc.subjectProgram voltage-
dc.subjectTrapped charge-
dc.subjectTrapped electrons-
dc.subjectFlash memory-
dc.titleEffects of nitride trap layer properties on location of charge centroid in charge-trap flash memory-
dc.typeArticle-
dc.type.rimsART-
dc.description.journalClass1-
dc.identifier.doi10.23919/SNW.2017.8242306-
dc.identifier.bibliographicCitation2017 Silicon Nanoelectronics Workshop, SNW 2017, v.2017-January, pp.79 - 80-
dc.identifier.scopusid2-s2.0-85051001839-
dc.citation.endPage80-
dc.citation.startPage79-
dc.citation.title2017 Silicon Nanoelectronics Workshop, SNW 2017-
dc.citation.volume2017-January-
dc.contributor.affiliatedAuthorYu, E.-
dc.contributor.affiliatedAuthorCho, S.-
dc.type.docTypeConference Paper-
dc.subject.keywordPlusCharge trapping-
dc.subject.keywordPlusNanoelectronics-
dc.subject.keywordPlusNitrides-
dc.subject.keywordPlusCharge centroid-
dc.subject.keywordPlusCharge trap flash memory-
dc.subject.keywordPlusElectron clouds-
dc.subject.keywordPlusFloating gates-
dc.subject.keywordPlusPolycrystalline-
dc.subject.keywordPlusProgram voltage-
dc.subject.keywordPlusTrapped charge-
dc.subject.keywordPlusTrapped electrons-
dc.subject.keywordPlusFlash memory-
dc.description.journalRegisteredClassscopus-
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