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Effect of channel thickness on the electrical performance and the stability of amorphous SiZnSnO thin film transistor

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dc.contributor.authorByun, Jae Min-
dc.contributor.authorLee, Sang Yeol-
dc.date.available2020-10-20T06:41:36Z-
dc.date.created2020-08-25-
dc.date.issued2020-10-
dc.identifier.issn1369-8001-
dc.identifier.urihttps://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/78452-
dc.description.abstractThe electrical performance and the stability of amorphous SiZnSnO (a-SZTO) thin film transistors (TFTs) were investigated depending on the channel thickness. The channel thickness was changed from 27 nm to 108 nm, systematically. As the channel thickness increased, the threshold voltage (V-TH) of a-SZTO shifted to the positive direction, from 2.13 to 4.59 V. The negative bias temperature stress test (NBTS) was measured at -20 V for 120 min to determine the stability of a-SZTO TFTs at 60 degrees C. The Delta V-TH was changed only 2.02 Vat 27 nm because of less total trap density in the channel layer. The mechanism of stability change depending on the thickness is explained. Transmission line method (TLM) was also used to find the relation between the total resistance (R-Total) and the channel thickness. As increasing the channel thickness, the contact resistance (R-C) increased and sheet resistance (R-sh) decreased. It must be considered the channel thickness of a-SZTO channel layer for the electrical properties and stability. Finally, we made the depletion load type inverter using two transistors of different channel thickness. The achieved voltage gain of the inverter is 21.962 V/V at the V-DD = 11 V.-
dc.language영어-
dc.language.isoen-
dc.publisherELSEVIER SCI LTD-
dc.relation.isPartOfMATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING-
dc.titleEffect of channel thickness on the electrical performance and the stability of amorphous SiZnSnO thin film transistor-
dc.typeArticle-
dc.type.rimsART-
dc.description.journalClass1-
dc.identifier.wosid000541163300020-
dc.identifier.doi10.1016/j.mssp.2020.105183-
dc.identifier.bibliographicCitationMATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, v.117-
dc.description.isOpenAccessN-
dc.citation.titleMATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING-
dc.citation.volume117-
dc.contributor.affiliatedAuthorLee, Sang Yeol-
dc.type.docTypeArticle-
dc.subject.keywordAuthorAmorphous oxide semiconductor thin film transistors-
dc.subject.keywordAuthorAmorphous silicon-zinc-tin-oxide-
dc.subject.keywordAuthorNegative bias temperature stress test-
dc.subject.keywordAuthorTransmission line method-
dc.subject.keywordAuthorDepletion load type inverter-
dc.subject.keywordPlusOXIDE SEMICONDUCTOR-
dc.subject.keywordPlusTEMPERATURE-
dc.subject.keywordPlusLAYER-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaMaterials Science-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryMaterials Science, Multidisciplinary-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.relation.journalWebOfScienceCategoryPhysics, Condensed Matter-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
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반도체대학 (반도체·전자공학부)
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