3레벨 4레그 PWM 컨버터의 커먼 모드 전압 저감Common-mode Voltage Reduction of Three Level Four Leg PWM Converter
- Other Titles
- Common-mode Voltage Reduction of Three Level Four Leg PWM Converter
- Authors
- 지승준; 고상기; 김현식; 설승기
- Issue Date
- Dec-2014
- Publisher
- 전력전자학회
- Keywords
- Pulse width modulation(PWM); Sinusoidal PWM(SPWM); Space-vector PWM(SVPWM); Digital signal processor(DSP); Common-mode voltage(CMV); Common-mode current(CMC)
- Citation
- 전력전자학회 논문지, v.19, no.6, pp.488 - 493
- Journal Title
- 전력전자학회 논문지
- Volume
- 19
- Number
- 6
- Start Page
- 488
- End Page
- 493
- URI
- https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/80346
- DOI
- 10.6113/TKPE.2014.19.6.488
- ISSN
- 1229-2214
- Abstract
- This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called “f leg pole voltage” is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%.
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