Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ansari, M.H.R. | - |
dc.contributor.author | Kannan, U.M. | - |
dc.contributor.author | Cho, Seongjae | - |
dc.date.accessioned | 2021-08-02T02:41:07Z | - |
dc.date.available | 2021-08-02T02:41:07Z | - |
dc.date.created | 2021-07-12 | - |
dc.date.issued | 2021-07 | - |
dc.identifier.issn | 2079-4991 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/81800 | - |
dc.description.abstract | This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depres-sion (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural net-work, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware. © 2021 by the authors. Licensee MDPI, Basel, Switzerland. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | MDPI | - |
dc.relation.isPartOf | Nanomaterials | - |
dc.title | Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000676651600001 | - |
dc.identifier.doi | 10.3390/nano11071773 | - |
dc.identifier.bibliographicCitation | Nanomaterials, v.11, no.7 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.scopusid | 2-s2.0-85109170631 | - |
dc.citation.title | Nanomaterials | - |
dc.citation.volume | 11 | - |
dc.citation.number | 7 | - |
dc.contributor.affiliatedAuthor | Ansari, M.H.R. | - |
dc.contributor.affiliatedAuthor | Kannan, U.M. | - |
dc.contributor.affiliatedAuthor | Cho, Seongjae | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Band-to-band tunneling | - |
dc.subject.keywordAuthor | Charge-trap synaptic transistor | - |
dc.subject.keywordAuthor | Long-term potentiation (LTP) | - |
dc.subject.keywordAuthor | Neural network | - |
dc.subject.keywordAuthor | Neuromorphic system | - |
dc.subject.keywordAuthor | Pattern recognition | - |
dc.subject.keywordAuthor | Short-term potentiation (STP) | - |
dc.subject.keywordPlus | FIELD-EFFECT TRANSISTOR | - |
dc.subject.keywordPlus | 1T DRAM | - |
dc.subject.keywordPlus | JUNCTIONLESS FET | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | SILICON | - |
dc.subject.keywordPlus | RETENTION | - |
dc.subject.keywordPlus | DEVICE | - |
dc.relation.journalResearchArea | Chemistry | - |
dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Chemistry, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Nanoscience & Nanotechnology | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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