Core-Shell Dual-Gate Nanowire Memory as a Synaptic Device for Neuromorphic Application
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ansari, M.H.R. | - |
dc.contributor.author | Cho, Seongjae | - |
dc.contributor.author | Lee, Jong-Ho | - |
dc.contributor.author | Park, Byung-Gook | - |
dc.date.accessioned | 2021-12-31T01:40:48Z | - |
dc.date.available | 2021-12-31T01:40:48Z | - |
dc.date.created | 2021-09-18 | - |
dc.date.issued | 2021-09 | - |
dc.identifier.issn | 2168-6734 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/83046 | - |
dc.description.abstract | In this work, a synaptic device for neuromorphic system is proposed and designed to emulate the biological behaviors in the novel device structure of core-shell dual-gate (CSDG) nanowire flash memory. Floating-body effect in the device and charge trapping/de-trapping in the nitride layer are found to be effective for short-term potentiation (STP), long-term potentiation (LTP), and long-term depression (LTD), respectively. STP realizes a temporary potentiation in the artificial neural network, and it can transit to LTP through the process of rehearsal and meaningful association. The transition takes place at the 10th pulse in a permissibly optimized CSDG synaptic device. The proposed device shows a stronger capacitive coupling between the dual gates, which forms a deeper potential well for charge storing and achieves better memory performance metrics such as sensing margin and retention time. The series of results reveal that the synaptic memory device is applicable to neuromorphic system due to the stronger gate controllability, multi-level weight adjustability, and Si processing compatibility. Author | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.relation.isPartOf | IEEE Journal of the Electron Devices Society | - |
dc.title | Core-Shell Dual-Gate Nanowire Memory as a Synaptic Device for Neuromorphic Application | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000728925500024 | - |
dc.identifier.doi | 10.1109/JEDS.2021.3111343 | - |
dc.identifier.bibliographicCitation | IEEE Journal of the Electron Devices Society, v.9, pp.1282 - 1289 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.scopusid | 2-s2.0-85114742940 | - |
dc.citation.endPage | 1289 | - |
dc.citation.startPage | 1282 | - |
dc.citation.title | IEEE Journal of the Electron Devices Society | - |
dc.citation.volume | 9 | - |
dc.contributor.affiliatedAuthor | Ansari, M.H.R. | - |
dc.contributor.affiliatedAuthor | Cho, Seongjae | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | core-shell dual-gate | - |
dc.subject.keywordAuthor | Depression | - |
dc.subject.keywordAuthor | Electric potential | - |
dc.subject.keywordAuthor | flash memory | - |
dc.subject.keywordAuthor | Logic gates | - |
dc.subject.keywordAuthor | long-term depression (LTD) | - |
dc.subject.keywordAuthor | long-term potentiation (LTP) | - |
dc.subject.keywordAuthor | Nanoscale devices | - |
dc.subject.keywordAuthor | nanowire | - |
dc.subject.keywordAuthor | neuromorphic system | - |
dc.subject.keywordAuthor | Performance evaluation | - |
dc.subject.keywordAuthor | short-term potentiation (STP) | - |
dc.subject.keywordAuthor | Si processing compatibility. | - |
dc.subject.keywordAuthor | Silicon | - |
dc.subject.keywordAuthor | synaptic device | - |
dc.subject.keywordAuthor | Tunneling | - |
dc.subject.keywordPlus | Charge trapping | - |
dc.subject.keywordPlus | Nanowires | - |
dc.subject.keywordPlus | Neural networks | - |
dc.subject.keywordPlus | Shells (structures) | - |
dc.subject.keywordPlus | Biological behavior | - |
dc.subject.keywordPlus | Capacitive couplings | - |
dc.subject.keywordPlus | Floating body effect | - |
dc.subject.keywordPlus | Long term depression | - |
dc.subject.keywordPlus | Long-term potentiations | - |
dc.subject.keywordPlus | Memory performance | - |
dc.subject.keywordPlus | Neuromorphic systems | - |
dc.subject.keywordPlus | Potential wells | - |
dc.subject.keywordPlus | Flash memory | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
1342, Seongnam-daero, Sujeong-gu, Seongnam-si, Gyeonggi-do, Republic of Korea(13120)031-750-5114
COPYRIGHT 2020 Gachon University All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.