A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Seo, Min-Jae | - |
dc.contributor.author | Jin, Dong-Hwan | - |
dc.contributor.author | Kim, Ye-Dam | - |
dc.contributor.author | Kim, Jong-Pal | - |
dc.contributor.author | Ryu, Seung-Tak | - |
dc.date.accessioned | 2022-03-07T05:40:12Z | - |
dc.date.available | 2022-03-07T05:40:12Z | - |
dc.date.created | 2022-03-06 | - |
dc.date.issued | 2020-10 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/83649 | - |
dc.description.abstract | This article presents a power-efficient buffer-embedding successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes a core power supply for the source-follower buffer, having a rail-to-rail signal swing due to the capacitive-level shifting bias scheme. Also, to implement the switched-capacitor (SC) level-shifting bias scheme without bias leakage issue, a negative boosting circuit is proposed. The boosting circuit is designed without any reliability issue, even with the use of thin-oxide transistors. For low-power applications, such as the biomedical system and CMOS image sensor, the proposed ADC incorporates a skip-reset (SR) scheme, a low-power delta-readout method. In conjunction with 8x oversampling and the power-saving SR technique that has inherent chopping capability, a prototype SAR ADC fabricated in a 180-nm CMOS technology achieves a peak 74.8-dB signal-to-noise and distortion ratio (SNDR) and an 89.1-dB spurious free dynamic range (SFDR) for a 640-kHz bandwidth (BW) with an oversampling ratio (OSR) of 8, resulting in a Schreier figure of merit (FoM) of 167.3 dB. The chip area occupies 0.192 mm(2), and the power consumption is 180.1 mu W. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.title | A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000572629500004 | - |
dc.identifier.doi | 10.1109/JSSC.2020.3006450 | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.55, no.10, pp.2660 - 2669 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.scopusid | 2-s2.0-85089372752 | - |
dc.citation.endPage | 2669 | - |
dc.citation.startPage | 2660 | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 55 | - |
dc.citation.number | 10 | - |
dc.contributor.affiliatedAuthor | Seo, Min-Jae | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Analog-to-digital converter (ADC) | - |
dc.subject.keywordAuthor | capacitive-level shifting | - |
dc.subject.keywordAuthor | delta (Delta) searching | - |
dc.subject.keywordAuthor | loop-embedded input buffer | - |
dc.subject.keywordAuthor | low power | - |
dc.subject.keywordAuthor | push-pull source follower (SF) | - |
dc.subject.keywordAuthor | skip-reset (SR) | - |
dc.subject.keywordAuthor | successive approximation register (SAR) | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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