A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration
DC Field | Value | Language |
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dc.contributor.author | Jo, Dong-Shin | - |
dc.contributor.author | Sung, Ba-Ro-Saim | - |
dc.contributor.author | Seo, Min-Jae | - |
dc.contributor.author | Kim, Woo-Cheol | - |
dc.contributor.author | Ryu, Seung-Tak | - |
dc.date.accessioned | 2022-03-07T05:40:15Z | - |
dc.date.available | 2022-03-07T05:40:15Z | - |
dc.date.created | 2022-03-06 | - |
dc.date.issued | 2020-04 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/83650 | - |
dc.description.abstract | This brief presents a 7-b 32-GS/s successive approximation register analog-to-digital converter (ADC) using a massive time-interleaving (TI) architecture. For low-skew multi-phase clocks, generation utilizing a delay-locked loop (DLL) phase-detector (PD) with a reduced offset is proposed to minimize skew between the clocks. Different clock path delays caused by distributed sub-ADCs over a large area in a massive TI-ADC are compensated for by multiplexing master clocks from the DLL. Offsets and skews in the sub-channels are calibrated on chip in the background via an additional dedicated sub-channel. A prototype chip was implemented in a 40-nm CMOS process with an active area of 0.36 mm(2). The measured SFDR and SNDR of the prototype ADC at a conversion rate of 32 GS/s are 43.1 and 31.4 dB, respectively. The ADC, including the input buffers, consumes 125 mW under a single 0.9-V supply. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.title | A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000522403100002 | - |
dc.identifier.doi | 10.1109/TCSII.2019.2916913 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.67, no.4, pp.610 - 614 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.scopusid | 2-s2.0-85082663921 | - |
dc.citation.endPage | 614 | - |
dc.citation.startPage | 610 | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.citation.volume | 67 | - |
dc.citation.number | 4 | - |
dc.contributor.affiliatedAuthor | Seo, Min-Jae | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Calibration | - |
dc.subject.keywordAuthor | Clocks | - |
dc.subject.keywordAuthor | Delays | - |
dc.subject.keywordAuthor | Circuits and systems | - |
dc.subject.keywordAuthor | Multiplexing | - |
dc.subject.keywordAuthor | Prototypes | - |
dc.subject.keywordAuthor | Analog-to-digital converter (ADC) | - |
dc.subject.keywordAuthor | time-interleaving | - |
dc.subject.keywordAuthor | massive | - |
dc.subject.keywordAuthor | successive approximation register (SAR) | - |
dc.subject.keywordAuthor | input buffer | - |
dc.subject.keywordAuthor | offset | - |
dc.subject.keywordAuthor | skew | - |
dc.subject.keywordAuthor | calibration | - |
dc.subject.keywordAuthor | DLL | - |
dc.subject.keywordAuthor | phase-detector (PD) | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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