A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs
DC Field | Value | Language |
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dc.contributor.author | Kim, Si-Nai | - |
dc.contributor.author | Kim, Woo-Cheol | - |
dc.contributor.author | Seo, Min-Jae | - |
dc.contributor.author | Ryu, Seung-Tak | - |
dc.date.accessioned | 2022-03-07T05:40:28Z | - |
dc.date.available | 2022-03-07T05:40:28Z | - |
dc.date.created | 2022-03-06 | - |
dc.date.issued | 2018-09 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/83654 | - |
dc.description.abstract | A 6-bit 20 GS/s two-channel time-interleaved current-steering digital-to-analog converter (DAC) with compact full-binary sub-DACs is presented. Optimally adjusted transition timings between the input data and the interleaving clock minimize glitches by the time-interleaving switches and enhance the high-frequency linearity. In order to prevent static linearity degradation by the leakage current through the time-interleaving switches, the relationship between the output current and the leakage current is analyzed. The proposed DAC architecture and the pseudo-differential logic gates for the high-speed data interface reduce the circuit complexity as well as the power consumption. The prototype 6-bit 20 GS/s DAC, fabricated in a 65-nm CMOS process, achieves a spurious-free dynamic range of 35.1 dB up to the Nyquist input, and consumes 136 mW given a 1.2-V power supply. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.title | A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000443055200006 | - |
dc.identifier.doi | 10.1109/TCSII.2018.2809965 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.9, pp.1154 - 1158 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.scopusid | 2-s2.0-85042848695 | - |
dc.citation.endPage | 1158 | - |
dc.citation.startPage | 1154 | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.citation.volume | 65 | - |
dc.citation.number | 9 | - |
dc.contributor.affiliatedAuthor | Seo, Min-Jae | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | DAC | - |
dc.subject.keywordAuthor | time-interleaving | - |
dc.subject.keywordAuthor | high-speed interface | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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