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RISC32-LP: Low-power FPGA-based IoT Sensor Nodes with Energy Reduction Program Analyzer

Authors
Tan, Beng-LiongMok, Kai-MingChang, Jing-JingLee, Wai-KongHwang, Seong Oun
Issue Date
15-Mar-2022
Publisher
Institute of Electrical and Electronics Engineers Inc.
Keywords
Clock Gating; Clocks; Dynamic Voltage and Frequency Scaling; Energy consumption; Energy Saving; Field Programmable Gate Array; Field programmable gate arrays; Hardware; Internet of Things; Internet of Things; Low Power; Power demand; Sensor Nodes.; Task analysis
Citation
IEEE Internet of Things Journal, v.9, no.6, pp.4214 - 4228
Journal Title
IEEE Internet of Things Journal
Volume
9
Number
6
Start Page
4214
End Page
4228
URI
https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/83811
DOI
10.1109/JIOT.2021.3103035
ISSN
2327-4662
Abstract
Field-Programmable Gate Array (FPGA)-based sensor nodes are popular for their flexible design approach and field reconfigurability. RISC32 is one of the recent Internet of Things (IoT) processors proposed for the development of FPGA-based sensor nodes, and it includes the ability to reconfigure the micro-architecture on the fly in order to reduce dynamic energy consumption. However, such a method does not minimize static energy consumption, which is important in FPGA-based systems. In this work, clock gating and dynamic voltage and frequency scaling are applied to further reduce the energy consumption in RISC32. In the research presented here, we implemented a new software called the Energy Reduction Program Analyser to estimate the parameters that configure a sensor node to achieve minimum energy consumption, targeting the typical IoT application scenario. Experimental results show that the low-power techniques applied in this work (RISC32-LP) can reduce energy consumption by 47%, compared to the standard RISC32 processor. IEEE
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College of IT Convergence (컴퓨터공학부(컴퓨터공학전공))
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