Area-optimized Constant-time Hardware Implementation for Polynomial Multiplication

Abstract

This work presents a lightweight, FPGA-based hardware implementation for polynomial multiplication, which is the major bottleneck in the NTRU public-key cryptographic scheme. NTRU is a quantum-resilient, lattice-based key exchange cryptosystem and is currently a finalist in the ongoing National Institute of Standards and Technology post-quantum cryptography standardization. It is challenging to fit these quantum-resilient schemes into IoT sensor nodes due to the strict resource constraints (smaller area, less memory, lower energy budgets) and the limited computational capabilities in embedded devices. We undertake this compact implementation for polynomial multiplication with two motivations: a) constant-time implementation ensuring inherent security against timing side-channel attacks, and b) optimized hardware consumption to make it suitable for IoT applications. A single-step multiplexer-based iterative architecture is proposed to achieve both goals simultaneously. Compared to the architectures presented in the literature, our proposed work eliminates the utilization of a modular arithmetic unit and replaces it with the correct selection of input followed by an accumulator, which can help to save substantial device resources. Experimental results with an FPGA show that our proposed architecture achieves an area reduction of up to 2.86× and the throughput increase up to 1.23× compared to the state-of-the-art implementation strategies, providing comparable latency along with an inherent-timing attack resilience that is absent in several NTRU hardware implementation schemes. IEEE