A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors
DC Field | Value | Language |
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dc.contributor.author | Lee, Chungryeol | - |
dc.contributor.author | Lee, Changhyeon | - |
dc.contributor.author | Lee, Seungmin | - |
dc.contributor.author | Choi, Junhwan | - |
dc.contributor.author | Yoo, Hocheon | - |
dc.contributor.author | Im, Sung Gap | - |
dc.date.accessioned | 2023-08-13T02:41:10Z | - |
dc.date.available | 2023-08-13T02:41:10Z | - |
dc.date.created | 2023-08-13 | - |
dc.date.issued | 2023-06 | - |
dc.identifier.issn | 2041-1723 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/88748 | - |
dc.description.abstract | A new type of heterojunction non-volatile memory transistor (H-MTR) has been developed, in which the negative transconductance (NTC) characteristics can be controlled systematically by a drain-aligned floating gate. In the H-MTR, a reliable transition between N-shaped transfer curves with distinct NTC and monolithically current-increasing transfer curves without apparent NTC can be accomplished through programming operation. Based on the H-MTR, a binary/ternary reconfigurable logic inverter (R-inverter) has been successfully implemented, which showed an unprecedentedly high static noise margin of 85% for binary logic operation and 59% for ternary logic operation, as well as long-term stability and outstanding cycle endurance. Furthermore, a ternary/binary dynamic logic conversion-in-memory has been demonstrated using a serially-connected R-inverter chain. The ternary/binary dynamic logic conversion-in-memory could generate three different output logic sequences for the same input signal in three logic levels, which is a new logic computing method that has never been presented before. Reconfigurable logic is desirable for high-density information processing. Here, the authors demonstrate a binary/ternary logic conversion-in-memory, which can operate in both binary and ternary logic systems to implement various types of logic gates. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | NATURE PORTFOLIO | - |
dc.relation.isPartOf | NATURE COMMUNICATIONS | - |
dc.title | A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 001018752400001 | - |
dc.identifier.doi | 10.1038/s41467-023-39394-5 | - |
dc.identifier.bibliographicCitation | NATURE COMMUNICATIONS, v.14, no.1 | - |
dc.description.isOpenAccess | Y | - |
dc.identifier.scopusid | 2-s2.0-85162750783 | - |
dc.citation.title | NATURE COMMUNICATIONS | - |
dc.citation.volume | 14 | - |
dc.citation.number | 1 | - |
dc.contributor.affiliatedAuthor | Yoo, Hocheon | - |
dc.type.docType | Article | - |
dc.subject.keywordPlus | ULTRATHIN | - |
dc.subject.keywordPlus | VOLTAGE | - |
dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
dc.relation.journalWebOfScienceCategory | Multidisciplinary Sciences | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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