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Optimized Memory System Architecture for VESA VDC-M Decoder with Multi-Slice SupportGo to Link

Yang, Hannah; Kim, Sohyeon; Kim, Saeyeon; Lee, Jiyoung; Roh, Huijin; Kim, Ji-Hoon

ArticleIssue Date2025CitationIEEE International Symposium on Circuits and Systems proceedings, pp 1 - 5
SCIESCOPUS
RISC-V Integrated Nested Loop Analyzer for Runtime DRAM Test Pattern GenerationGo to Link

Kim, Saeyeon; Park, Sunyoung; Kim, Nahyeon; Lee, Jiyoung; Kim, Ji-Hoon

ArticleIssue Date2025CitationIEEE Embedded Systems Letters, v.17, no.5, pp 333 - 336PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
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