RISC-V Integrated Nested Loop Analyzer for Runtime DRAM Test Pattern Generation

Abstract

Recent advancements in DRAM technology have increased the complexity and variety of memory faults, necessitating efficient and programmable fault diagnosis, especially in AI and automotive systems where reliability is critical. This letter proposes a Nested Loop Analyzer (NLA) integrated into a RISC-V-based memory test platform to enhance both efficiency and programmability in run-time memory testing. By leveraging Loop Control Flow Analysis and Basic Block Identification, the NLA eliminates complex loop control in pattern generation and reduces pattern buffer overhead between the Pattern Generator (PG) and the DRAM physical layer (PHY). Additionally, integrating memory testing within the RISC-V system-on-chip (SoC) environment enables seamless development and integration of memory testing with general application tasks. The proposed approach provides a high-programmability, run-time DRAM test pattern generation platform with efficient hardware usage, reduced buffer requirements, and seamless RISC-V integration.