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Effects of Grain Size on the Electrical Characteristics of Three-Dimensional NAND Flash Memory Devices

Authors
Lee, Jun GyuKIM, TAE WHAN
Issue Date
Oct-2019
Publisher
AMER SCIENTIFIC PUBLISHERS
Keywords
Vertical NAND Flash Memory; Polysilicon Channel; Charge Trapping Layer; Threshold Voltage Shift
Citation
JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v.19, no.10, pp.6202 - 6205
Indexed
SCIE
Journal Title
JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY
Volume
19
Number
10
Start Page
6202
End Page
6205
URI
https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/12436
DOI
10.1166/jnn.2019.17015
ISSN
1533-4880
Abstract
Polysilicon is commonly used as the channel in three-dimensional (3D) NAND flash memory devices. However, degradation of device performance due to grain boundary traps in the channel is a major issue. The saturation on-current level, threshold voltage (V-th), and electron density of 3D NAND flash memory devices with randomly generated grain boundaries were investigated by using three-dimensional technology computer-aided design (TCAD) simulation. The device performance tended to degrade with an increasing number of grains, and the direction of the grains significantly affected the device performance. The large decrease in the electron density of the channel region due to the direction of the grains can be explained according to the formation of the depletion region.
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