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Two-level differential burn-in policy for spatially heterogeneous defect units in semiconductor manufacturing

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dc.contributor.authorChen, Yuan-
dc.contributor.authorYuan, Tao-
dc.contributor.authorBae, Suk Joo-
dc.contributor.authorKuo, Yue-
dc.date.accessioned2022-07-06T11:07:05Z-
dc.date.available2022-07-06T11:07:05Z-
dc.date.created2021-12-08-
dc.date.issued2021-12-
dc.identifier.issn0360-8352-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/140192-
dc.description.abstractBurn-in (BI) is an effective technique in semiconductor manufacturing to weed out defective devices. BI has been generally conducted on all of packaged devices for the same duration. Realizing that devices in the BI population usually have different reliability at various production levels, this study proposes a new two-level differential BI policy and two BI optimization models to determine the cost-optimal and profit-optimal BI decisions, respectively. The BI tests are conducted at two production levels: wafer-level (WL) and package-level (PL). After a common wafer-level BI for all devices, survival devices are subject to three different decisions: rejection without PLBI, acceptance without PLBI, and test with PLBI. The cost objective function consists of the BI test costs, BI failure costs, and warranty failure cost, while the profit objective function considers the manufacturing costs, BI test costs, warranty failure cost, revenue, and yield loss. Spatially varying yield and probability with reliability defects are computed via spatial regression modeling of clustered defect counts. Two numerical examples are used to illustrate the proposed BI policy and models based on the spatial defects modeling. Analytical results demonstrate that the two-level differential BI policy can be a cost- and profit-effective alternative over the conventional single PLBI policy.-
dc.language영어-
dc.language.isoen-
dc.publisherPERGAMON-ELSEVIER SCIENCE LTD-
dc.titleTwo-level differential burn-in policy for spatially heterogeneous defect units in semiconductor manufacturing-
dc.typeArticle-
dc.contributor.affiliatedAuthorBae, Suk Joo-
dc.identifier.doi10.1016/j.cie.2021.107768-
dc.identifier.scopusid2-s2.0-85118557319-
dc.identifier.wosid000720350800011-
dc.identifier.bibliographicCitationCOMPUTERS & INDUSTRIAL ENGINEERING, v.162, pp.1 - 12-
dc.relation.isPartOfCOMPUTERS & INDUSTRIAL ENGINEERING-
dc.citation.titleCOMPUTERS & INDUSTRIAL ENGINEERING-
dc.citation.volume162-
dc.citation.startPage1-
dc.citation.endPage12-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryComputer Science, Interdisciplinary Applications-
dc.relation.journalWebOfScienceCategoryEngineering, Industrial-
dc.subject.keywordPlusNUMBER-
dc.subject.keywordAuthorBurn-in-
dc.subject.keywordAuthorCost optimization-
dc.subject.keywordAuthorNonhomogeneous Poisson process-
dc.subject.keywordAuthorReliability defects-
dc.subject.keywordAuthorSpatial modeling-
dc.subject.keywordAuthorYield-
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