Understanding and Reducing Weight-Load Overhead of Systolic Deep Learning Accelerators
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Joo, JinWon | - |
dc.contributor.author | Yoon, Minyong | - |
dc.contributor.author | Choi, Jung wook | - |
dc.contributor.author | Kang, Mingu | - |
dc.contributor.author | Lee, JongGeon | - |
dc.contributor.author | So, JinIn | - |
dc.contributor.author | Yun, IlKwon | - |
dc.contributor.author | Kwon, Yongsuk | - |
dc.contributor.author | Kim, KyungSoo | - |
dc.date.accessioned | 2022-07-06T11:33:15Z | - |
dc.date.available | 2022-07-06T11:33:15Z | - |
dc.date.created | 2022-03-07 | - |
dc.date.issued | 2021-11 | - |
dc.identifier.issn | 2163-9612 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/140372 | - |
dc.description.abstract | As an energy-efficient computing engine for deep neural network inference, 2D systolic array architectures have been widely adopted in modern deep learning accelerators. However, despite high compute density and energy-efficient data passing, systolic accelerators suffer a non-Trivial overhead of loading data stationed inside their local register file. This loading overhead becomes a critical issue when a frequent reload of stationary data (e.g., weight parameters) is required. This paper proposes a simple yet practical SW-HW co-optimization that reverses the weight-load order and adds a dedicated path for weight-load. On diverse deep learning applications, the proposed method reduces the weight-load overhead and achieves up to 1.8× speedup with 40% energy savings. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.title | Understanding and Reducing Weight-Load Overhead of Systolic Deep Learning Accelerators | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Choi, Jung wook | - |
dc.identifier.doi | 10.1109/ISOCC53507.2021.9613929 | - |
dc.identifier.scopusid | 2-s2.0-85123361135 | - |
dc.identifier.wosid | 000861550500176 | - |
dc.identifier.bibliographicCitation | Proceedings - International SoC Design Conference 2021, ISOCC 2021, pp.413 - 414 | - |
dc.relation.isPartOf | Proceedings - International SoC Design Conference 2021, ISOCC 2021 | - |
dc.citation.title | Proceedings - International SoC Design Conference 2021, ISOCC 2021 | - |
dc.citation.startPage | 413 | - |
dc.citation.endPage | 414 | - |
dc.type.rims | ART | - |
dc.type.docType | Proceedings Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | Acceleration | - |
dc.subject.keywordPlus | Computer aided design | - |
dc.subject.keywordPlus | Cost reduction | - |
dc.subject.keywordPlus | Energy efficiency | - |
dc.subject.keywordPlus | Low power electronics | - |
dc.subject.keywordPlus | Network architecture | - |
dc.subject.keywordPlus | Systolic arrays | - |
dc.subject.keywordPlus | Computing engines | - |
dc.subject.keywordPlus | Critical issues | - |
dc.subject.keywordPlus | Energy efficient | - |
dc.subject.keywordPlus | Energy-efficient computing | - |
dc.subject.keywordPlus | Loading data | - |
dc.subject.keywordPlus | Network inference | - |
dc.subject.keywordPlus | Non-trivial | - |
dc.subject.keywordPlus | Register files | - |
dc.subject.keywordPlus | Systolic array architecture | - |
dc.subject.keywordPlus | Weight parameters | - |
dc.subject.keywordPlus | Deep neural networks | - |
dc.subject.keywordAuthor | accelerator | - |
dc.subject.keywordAuthor | deep neural network | - |
dc.subject.keywordAuthor | systolic array | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/9613929 | - |
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