Understanding and Reducing Weight-Load Overhead of Systolic Deep Learning Accelerators
- Authors
- Joo, JinWon; Yoon, Minyong; Choi, Jung wook; Kang, Mingu; Lee, JongGeon; So, JinIn; Yun, IlKwon; Kwon, Yongsuk; Kim, KyungSoo
- Issue Date
- Nov-2021
- Publisher
- IEEE
- Keywords
- accelerator; deep neural network; systolic array
- Citation
- Proceedings - International SoC Design Conference 2021, ISOCC 2021, pp.413 - 414
- Indexed
- SCOPUS
- Journal Title
- Proceedings - International SoC Design Conference 2021, ISOCC 2021
- Start Page
- 413
- End Page
- 414
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/140372
- DOI
- 10.1109/ISOCC53507.2021.9613929
- ISSN
- 2163-9612
- Abstract
- As an energy-efficient computing engine for deep neural network inference, 2D systolic array architectures have been widely adopted in modern deep learning accelerators. However, despite high compute density and energy-efficient data passing, systolic accelerators suffer a non-Trivial overhead of loading data stationed inside their local register file. This loading overhead becomes a critical issue when a frequent reload of stationary data (e.g., weight parameters) is required. This paper proposes a simple yet practical SW-HW co-optimization that reverses the weight-load order and adds a dedicated path for weight-load. On diverse deep learning applications, the proposed method reduces the weight-load overhead and achieves up to 1.8× speedup with 40% energy savings.
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