Design Techniques for Area-efficient Two-Stacked Current Sources in Nanometer CMOS Technology

Abstract

Employing long-channel transistors for building current sources increases the analog circuit area because of complicated design rules associated with the use of long channel transistors, especially in advanced CMOS technologies. Therefore, stacked short-channel transistors are preferred for current source construction; however, they require proper design techniques. In this paper, we propose two-stacked current source design techniques, along with small-and large-signal graphical analyses. The results reveal that two-stacked current sources can achieve high output resistance and high current density with a properly determined width ratio.