Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Heechun | - |
dc.contributor.author | Chang, Kyungjoon | - |
dc.contributor.author | Jeong, Jooyeon | - |
dc.contributor.author | Ahn, Jaehoon | - |
dc.contributor.author | Chung, Ki-Seok | - |
dc.contributor.author | KIM, Taewhan | - |
dc.date.accessioned | 2022-07-06T11:33:29Z | - |
dc.date.available | 2022-07-06T11:33:29Z | - |
dc.date.created | 2022-03-07 | - |
dc.date.issued | 2021-11 | - |
dc.identifier.issn | 2163-9612 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/140378 | - |
dc.description.abstract | Design-Technology-co-optimization (DTCO) is essential in deep submicron technologies (e.g., 14nm and below) to co-optimize process technology and design rules and obtain more benefit from advanced node. As the process technology shrinks to deep submicron, the importance of back-end-of-line (BEOL) interconnect in a full chip design drastically grows since its less-Than-micron width brings unexpected critical design rules that requires novel design techniques. In this paper, we provide a comprehensive survey on recent challenging issues and cutting-edge design methodologies for DTCO in deep submicron interconnect technology, which includes: offset assignment for pin accessibility; monolithic 3D integration; middle-of-line (MOL) utilization for routing; BEOL-Aware representative critical path circuit synthesis; and buried power rail (BPR). | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.title | Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | KIM, Taewhan | - |
dc.identifier.doi | 10.1109/ISOCC53507.2021.9614026 | - |
dc.identifier.scopusid | 2-s2.0-85123382745 | - |
dc.identifier.wosid | 000861550500096 | - |
dc.identifier.bibliographicCitation | Proceedings - International SoC Design Conference 2021, ISOCC 2021, pp.215 - 218 | - |
dc.relation.isPartOf | Proceedings - International SoC Design Conference 2021, ISOCC 2021 | - |
dc.citation.title | Proceedings - International SoC Design Conference 2021, ISOCC 2021 | - |
dc.citation.startPage | 215 | - |
dc.citation.endPage | 218 | - |
dc.type.rims | ART | - |
dc.type.docType | Proceedings Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | Computer aided design | - |
dc.subject.keywordPlus | Three dimensional integrated circuits | - |
dc.subject.keywordPlus | Co-optimization | - |
dc.subject.keywordPlus | Deep sub-micron | - |
dc.subject.keywordPlus | Deep submicron technology | - |
dc.subject.keywordPlus | Deep submicrons | - |
dc.subject.keywordPlus | Design rules | - |
dc.subject.keywordPlus | Design technologies | - |
dc.subject.keywordPlus | Interconnect technology | - |
dc.subject.keywordPlus | Optimization methodology | - |
dc.subject.keywordPlus | Process Technologies | - |
dc.subject.keywordPlus | Sub-micron interconnect | - |
dc.subject.keywordPlus | Integrated circuit interconnects | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/9614026 | - |
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