High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Sung, Gaeryun | - |
dc.contributor.author | Han, Jae duk | - |
dc.date.accessioned | 2022-07-06T11:33:32Z | - |
dc.date.available | 2022-07-06T11:33:32Z | - |
dc.date.created | 2022-03-07 | - |
dc.date.issued | 2021-11 | - |
dc.identifier.issn | 2163-9612 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/140379 | - |
dc.description.abstract | This paper presents a high-speed strongARM-latch-based bang-bang phase detector (PD). Instead of using D-flipflops (DFF) or D-latches, which are used in conventional bang-bang PDs, strongARM latches are used to achieve high sensitivity owing to their regeneration behaviors. By comparing the clock-To-Q delay(tcq) and maximum data rate of conventional and proposed phase detectors, it is found that the proposed strongARM-latch-based bang-bang PD has a smaller clock-To-Q delay and a higher data rate. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.title | High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Han, Jae duk | - |
dc.identifier.doi | 10.1109/ISOCC53507.2021.9613931 | - |
dc.identifier.scopusid | 2-s2.0-85123382931 | - |
dc.identifier.wosid | 000861550500162 | - |
dc.identifier.bibliographicCitation | Proceedings - International SoC Design Conference 2021, ISOCC 2021, pp.377 - 378 | - |
dc.relation.isPartOf | Proceedings - International SoC Design Conference 2021, ISOCC 2021 | - |
dc.citation.title | Proceedings - International SoC Design Conference 2021, ISOCC 2021 | - |
dc.citation.startPage | 377 | - |
dc.citation.endPage | 378 | - |
dc.type.rims | ART | - |
dc.type.docType | Proceedings Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | clock-To-Q delay | - |
dc.subject.keywordAuthor | phase detector | - |
dc.subject.keywordAuthor | power consumption | - |
dc.subject.keywordAuthor | StorngARM latch | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/9613931 | - |
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