Impact of Residual Stress on a Polysilicon Channel in Scaled 3D NAND Flash Memory

Abstract

The effects of residual stress on a tungsten gate in a polysilicon channel in scaled 3D NAND flash memories were investigated using a technology computer-aided design simulation. The NAND strings, with respect to the distance from the tungsten slit, were also analyzed. The scaling of the spacer thickness and hole diameter induced compressive stress on the polysilicon channel. Moreover, the residual stress of polysilicon channel in the string near the tungsten slit had greater compressive stress than the string farther away. The increase in compressive stress in the polysilicon channel degraded the Bit-Line current (I-on) due to stress-induced electron mobility deterioration. Moreover, a threshold voltage shift ( increment V-th) occurred in the negative direction due to conduction band lowering.