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Iterative Pseudo-Soft-Reliability-based Majority-Logic Decoding for NAND Flash Memory
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Park, KB | - |
| dc.contributor.author | Chung, K | - |
| dc.date.accessioned | 2022-07-06T18:20:31Z | - |
| dc.date.available | 2022-07-06T18:20:31Z | - |
| dc.date.created | 2021-07-14 | - |
| dc.date.issued | 2021-05 | - |
| dc.identifier.issn | 2169-3536 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/141929 | - |
| dc.description.abstract | This paper proposes a decoding algorithm for nonbinary low-density parity-check (NB-LDPC) codes, aiming to improve the error rate performance for NAND flash memory. Several NB-LDPC decoding methods for NAND flash memory have been studied. Some approaches rely on hard decisions, and these are relatively simple but do not have a good error rate performance. Others are based on soft decisions that require multiple reads for each flash memory cell, leading to significant memory throughput degradation. To improve the error rate performance without suffering performance degradation owing to multiple reads, an iterative pseudo-soft-reliability-based decoding algorithm is proposed. Using Galois field addition to calculate the Hamming distance at the initialization, the proposed algorithm not only improves the error rate performance but also reduces the average number of iterations compared with those of conventional hard-decision-based decoding algorithms. CCBY | - |
| dc.language | 영어 | - |
| dc.language.iso | en | - |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
| dc.title | Iterative Pseudo-Soft-Reliability-based Majority-Logic Decoding for NAND Flash Memory | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | Chung, K | - |
| dc.identifier.doi | 10.1109/ACCESS.2021.3079939 | - |
| dc.identifier.scopusid | 2-s2.0-85105879825 | - |
| dc.identifier.wosid | 000673584600001 | - |
| dc.identifier.bibliographicCitation | IEEE Access, v.9, pp.74531 - 74538 | - |
| dc.relation.isPartOf | IEEE Access | - |
| dc.citation.title | IEEE Access | - |
| dc.citation.volume | 9 | - |
| dc.citation.startPage | 74531 | - |
| dc.citation.endPage | 74538 | - |
| dc.type.rims | ART | - |
| dc.type.docType | Article in Press | - |
| dc.description.journalClass | 1 | - |
| dc.description.isOpenAccess | Y | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Computer Science | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalResearchArea | Telecommunications | - |
| dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.relation.journalWebOfScienceCategory | Telecommunications | - |
| dc.subject.keywordPlus | Errors | - |
| dc.subject.keywordPlus | Flash memory | - |
| dc.subject.keywordPlus | Hamming distance | - |
| dc.subject.keywordPlus | Majority logic | - |
| dc.subject.keywordPlus | Memory architecture | - |
| dc.subject.keywordPlus | NAND circuits | - |
| dc.subject.keywordPlus | Turbo codes | - |
| dc.subject.keywordPlus | Decoding algorithm | - |
| dc.subject.keywordPlus | Error rate performance | - |
| dc.subject.keywordPlus | Flash memory cell | - |
| dc.subject.keywordPlus | Low density parity check | - |
| dc.subject.keywordPlus | Majority logic decoding | - |
| dc.subject.keywordPlus | NAND flash memory | - |
| dc.subject.keywordPlus | Performance degradation | - |
| dc.subject.keywordPlus | Throughput degradation | - |
| dc.subject.keywordPlus | Iterative decoding | - |
| dc.subject.keywordAuthor | Complexity theory | - |
| dc.subject.keywordAuthor | Decoding | - |
| dc.subject.keywordAuthor | Error analysis | - |
| dc.subject.keywordAuthor | Error correction codes | - |
| dc.subject.keywordAuthor | Hamming distance | - |
| dc.subject.keywordAuthor | Hamming distance | - |
| dc.subject.keywordAuthor | Hard decision | - |
| dc.subject.keywordAuthor | Iterative decoding | - |
| dc.subject.keywordAuthor | Iterative hard-reliability-based majority-logic decoding algorithm | - |
| dc.subject.keywordAuthor | NAND flash memory | - |
| dc.subject.keywordAuthor | Nonbinary low-density parity-check codes | - |
| dc.subject.keywordAuthor | Prediction algorithms | - |
| dc.subject.keywordAuthor | Reliability | - |
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