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Statistical Models of Overdispersed Spatial Defects for Predicting the Yield of Integrated Circuits

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dc.contributor.authorYuan, Tao-
dc.contributor.authorBae, Suk Joo-
dc.contributor.authorKuo, Yue-
dc.date.accessioned2022-07-08T00:46:09Z-
dc.date.available2022-07-08T00:46:09Z-
dc.date.issued2020-06-
dc.identifier.issn0018-9529-
dc.identifier.issn1558-1721-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/145595-
dc.description.abstractDefects generated in semiconductor manufacturing processes have serious effects on the yield of integrated circuits (ICs). Accurate modeling of the defect counts on IC chips is crucial for predicting the yield. The conventional Poisson yield model tends to underestimate the true yield by ignoring overdispersed patterns of defects on the wafer. This article uses various models based on the generalized Poisson (GP) distribution and/or HZ distributions to explore the overdispersed defect counts on semiconductor wafers. Real wafer map data are used to compare the performance of both nonregression and regression modeling approaches in terms of the log-likelihood, AIC, and relative bias for yield estimation. Analytical results indicate that the GP distribution is a competitive alternative to the negative binomial (NB) distribution for modeling defect counts on IC chips because the GP distribution can model overdispersion, underdispersion, or no dispersion. In particular, HZ models based on the NB and GP distributions show good potential for predicting the yield of IC chips on wafers.-
dc.format.extent12-
dc.language영어-
dc.language.isoENG-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.titleStatistical Models of Overdispersed Spatial Defects for Predicting the Yield of Integrated Circuits-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1109/TR.2019.2943925-
dc.identifier.scopusid2-s2.0-85086767510-
dc.identifier.wosid000543025000008-
dc.identifier.bibliographicCitationIEEE Transactions on Reliability, v.69, no.2, pp 510 - 521-
dc.citation.titleIEEE Transactions on Reliability-
dc.citation.volume69-
dc.citation.number2-
dc.citation.startPage510-
dc.citation.endPage521-
dc.type.docTypeArticle-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryComputer Science, Software Engineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusZERO-INFLATED POISSON-
dc.subject.keywordPlusREGRESSION-
dc.subject.keywordPlusCOUNTS-
dc.subject.keywordAuthorIntegrated circuit modeling-
dc.subject.keywordAuthorSemiconductor device modeling-
dc.subject.keywordAuthorPredictive models-
dc.subject.keywordAuthorDispersion-
dc.subject.keywordAuthorManufacturing-
dc.subject.keywordAuthorClustered defects-
dc.subject.keywordAuthorgeneralized Poisson (GP) distribution-
dc.subject.keywordAuthorhurdle-at-zero (HZ) models-
dc.subject.keywordAuthormaximum likelihood estimation-
dc.subject.keywordAuthorprediction of IC yield-
dc.subject.keywordAuthorzero-inflated models-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8870199-
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