Optimizing a FPGA-based neural accelerator for small IoT devices
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hong, Seongmin | - |
dc.contributor.author | Lee, Inho | - |
dc.contributor.author | Park, Yongjun | - |
dc.date.accessioned | 2022-07-12T06:11:54Z | - |
dc.date.available | 2022-07-12T06:11:54Z | - |
dc.date.created | 2021-05-11 | - |
dc.date.issued | 2018-04 | - |
dc.identifier.issn | 0000-0000 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/150324 | - |
dc.description.abstract | As neural networks have been widely used for machine-learning algorithms such as image recognition, to design efficient neural accelerators has recently become more important. However, designing neural accelerators is generally difficult because of their high memory storage requirement. In this paper, we propose an area-and-power efficient neural accelerator for small IoT devices, using 4-bit fixed-point weights through quantization technique. The proposed neural accelerator is trained through the TensorFlow infrastructure and the weight data is optimized in order to reduce the overhead of high weight memory requirement. Our FPGA-based design achieves 97.44% accuracy with MNIST 10,000 test images. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | Optimizing a FPGA-based neural accelerator for small IoT devices | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Yongjun | - |
dc.identifier.doi | 10.23919/ELINFOCOM.2018.8330546 | - |
dc.identifier.scopusid | 2-s2.0-85048549679 | - |
dc.identifier.bibliographicCitation | International Conference on Electronics, Information and Communication, ICEIC 2018, v.2018-January, pp.1 - 2 | - |
dc.relation.isPartOf | International Conference on Electronics, Information and Communication, ICEIC 2018 | - |
dc.citation.title | International Conference on Electronics, Information and Communication, ICEIC 2018 | - |
dc.citation.volume | 2018-January | - |
dc.citation.startPage | 1 | - |
dc.citation.endPage | 2 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | Digital storage | - |
dc.subject.keywordPlus | Field programmable gate arrays (FPGA) | - |
dc.subject.keywordPlus | Image recognition | - |
dc.subject.keywordPlus | Integrated circuit design | - |
dc.subject.keywordPlus | Internet of things | - |
dc.subject.keywordPlus | Learning algorithms | - |
dc.subject.keywordPlus | Learning systems | - |
dc.subject.keywordPlus | Neural networks | - |
dc.subject.keywordPlus | Particle accelerators | - |
dc.subject.keywordPlus | Fixed points | - |
dc.subject.keywordPlus | Iot devices | - |
dc.subject.keywordPlus | Memory requirements | - |
dc.subject.keywordPlus | Memory storage | - |
dc.subject.keywordPlus | Power efficient | - |
dc.subject.keywordPlus | Quantization | - |
dc.subject.keywordPlus | Test images | - |
dc.subject.keywordPlus | Acceleration | - |
dc.subject.keywordAuthor | Accelerator | - |
dc.subject.keywordAuthor | FPGA | - |
dc.subject.keywordAuthor | Neural networks | - |
dc.subject.keywordAuthor | Quantization | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/8330546 | - |
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