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Analysis of various DRAM devices from power consumption's perspective

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dc.contributor.authorJeon, Dong-Ik-
dc.contributor.authorLee, Min-Kyu-
dc.contributor.authorChung, Ki-Seok-
dc.date.accessioned2022-07-15T21:40:55Z-
dc.date.available2022-07-15T21:40:55Z-
dc.date.created2021-05-13-
dc.date.issued2015-08-
dc.identifier.issn0000-0000-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/156617-
dc.description.abstractDRAM has become a crucial component in terms of system power consumption as the size of main memory increases. To improve power efficiency of DRAM devices, we need to analyze characteristics of DRAM behavior from power consumption's perspective. In this paper, we analyze the characteristics of various DRAM devices from major vendors under real system operating environment. As the size of the DRAM increases, power consumption due to activate, precharge and burst operations remains about the same, but that due to background and refresh operations increases steadily. Especially, power consumption due to the refresh operation for 3D stacked DRAMs increases by 91% at high temperatures, which strongly implies that the refresh operation will become more crucial for DRAMs in the future.-
dc.language영어-
dc.language.isoen-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleAnalysis of various DRAM devices from power consumption's perspective-
dc.typeArticle-
dc.contributor.affiliatedAuthorChung, Ki-Seok-
dc.identifier.doi10.1109/NAS.2015.7255229-
dc.identifier.scopusid2-s2.0-84960850915-
dc.identifier.bibliographicCitationProceedings of the 2015 IEEE International Conference on Networking, Architecture and Storage, NAS 2015, pp.359 - 360-
dc.relation.isPartOfProceedings of the 2015 IEEE International Conference on Networking, Architecture and Storage, NAS 2015-
dc.citation.titleProceedings of the 2015 IEEE International Conference on Networking, Architecture and Storage, NAS 2015-
dc.citation.startPage359-
dc.citation.endPage360-
dc.type.rimsART-
dc.type.docTypeConference Paper-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscopus-
dc.subject.keywordPlusElectric power utilization-
dc.subject.keywordPlusEnergy efficiency-
dc.subject.keywordPlusMemory architecture-
dc.subject.keywordPlusThree dimensional integrated circuits-
dc.subject.keywordPlus3d-stacked drams-
dc.subject.keywordPlusAnalysis of various-
dc.subject.keywordPlusHigh temperature-
dc.subject.keywordPlusMain memory-
dc.subject.keywordPlusOperating environment-
dc.subject.keywordPlusPower analysis-
dc.subject.keywordPlusPower efficiency-
dc.subject.keywordPlusrefresh-
dc.subject.keywordPlusDynamic random access storage-
dc.subject.keywordAuthorDRAM-
dc.subject.keywordAuthormain memory-
dc.subject.keywordAuthorpower analysis-
dc.subject.keywordAuthorrefresh-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/7255229-
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