3차원 구조의 NAND flash memory에서 적층수 증가에 따른 문턱전압 산포 문제에 대한 연구

Abstract

According to Moor‘s law, Scaling of memory was continued but scaling of tow-dimensional structure was reached the limit at 10nm process. Consequently three-dimensional structure was discussed and produced. Nowadays 24 stacks memory was produced. But we need to study problem that is generated by continued increasing of stack for improving integration. We composed BiCS structure with previously discussed three-dimensional structure. And we found problem that occur according to increasing stacks level in one string from changing characteristic of drain current following gate voltage changing. In this paper, we describe improvement direction of occurrence problem by the above analysis.