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An efficient check node operation circuit for Min-Sum based LDPC decoder
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Cho, Keol | - |
| dc.contributor.author | Chung, Ki-Seok | - |
| dc.date.accessioned | 2022-07-16T05:29:34Z | - |
| dc.date.available | 2022-07-16T05:29:34Z | - |
| dc.date.created | 2021-05-11 | - |
| dc.date.issued | 2014-04 | - |
| dc.identifier.issn | 0000-0000 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/160351 | - |
| dc.description.abstract | This paper presents a low power and area-efficient check node operation circuit for LDPC decoders based on Min-Sum algorithm. By improving a heavily used comparator circuit, our proposed check node unit reduces area and power consumption by 8% and 13%, respectively, without decoding speed degradation compared to conventional LDPC decoders. | - |
| dc.language | 영어 | - |
| dc.language.iso | en | - |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
| dc.title | An efficient check node operation circuit for Min-Sum based LDPC decoder | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | Chung, Ki-Seok | - |
| dc.identifier.doi | 10.1109/ISCE.2014.6884452 | - |
| dc.identifier.scopusid | 2-s2.0-84907412654 | - |
| dc.identifier.bibliographicCitation | Proceedings of the International Symposium on Consumer Electronics, ISCE, pp.1 - 2 | - |
| dc.relation.isPartOf | Proceedings of the International Symposium on Consumer Electronics, ISCE | - |
| dc.citation.title | Proceedings of the International Symposium on Consumer Electronics, ISCE | - |
| dc.citation.startPage | 1 | - |
| dc.citation.endPage | 2 | - |
| dc.type.rims | ART | - |
| dc.type.docType | Conference Paper | - |
| dc.description.journalClass | 1 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.subject.keywordPlus | Algorithms | - |
| dc.subject.keywordPlus | Consumer electronics | - |
| dc.subject.keywordPlus | Decoding | - |
| dc.subject.keywordPlus | Area-Efficient | - |
| dc.subject.keywordPlus | Check node units | - |
| dc.subject.keywordPlus | Circuit size | - |
| dc.subject.keywordPlus | Decoding speed | - |
| dc.subject.keywordPlus | LDPC decoder | - |
| dc.subject.keywordPlus | Low Power | - |
| dc.subject.keywordPlus | Low-density parity-check (LDPC) codes | - |
| dc.subject.keywordPlus | Min-Sum algorithm | - |
| dc.subject.keywordPlus | Low power electronics | - |
| dc.subject.keywordAuthor | circuit size | - |
| dc.subject.keywordAuthor | LDPC decoder | - |
| dc.subject.keywordAuthor | low power | - |
| dc.subject.keywordAuthor | low-density parity-check codes | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/6884452 | - |
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Related Researcher
- Chung, Ki Seok
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)