Increased memory performance of a Pi (I broken vertical bar) gate structure in a 3-D stackable vertical gate NAND flash memory

Abstract

In this study, we propose a pi(I broken vertical bar)-gate structure that improves the performance of vertical gate (VG) NAND flash memory structures. The pi-gate (PG) structure extends the gates along the top and the bottom surfaces of the silicon layer, widening the channel width and resulting in an increased device current. The extended gates also enhance gate coupling with the channel by allowing more of the gate field to interact with the channel, giving lower threshold voltages (20% reduction) and lower subthreshold swings (21% reduction) and greatly enhancing the switching characteristics. Also, a PG width of 18 nm resulted in an increase in the programmed threshold voltage shift of 39% compared to that of the conventional VG-NAND structure. The PG structured VG-NAND may allow a non-volatile memory to be further integrated by giving solutions to the high channel resistance and reduced memory performance issues related to integration in vertical dimensions.