Parallelization of Turbo decoder and Its Implementation on GPU for SDR-based LTE system

Abstract

In this paper, we first presented a parallelized turbo decoding algorithm, which is widely used as a tool for FEC(Forward Error Correction). Then, the proposed parallelized algorithm was implemented on a GPU(Graphic Processor Unit) board. We analyzed the performance of implemented turbo decoder on a SDR(Software Defined Radio)-based LTE(Long Term Evolution) system. Turbo code is one type of error correcting codes, which is an efficient countermeasure against errors occurred by noise, fading, and interference generated in various kinds of adverse communication channels. For that reason, turbo codes have been adopted in many communication standards such as WiMAX(Worldwide Interoperability for Microwave Access), WCDMA(Wideband Code Division Multiple Access), LTE, etc. However, since the MAP(maximum a posteriori) decoder, which is a core part of turbo decoder, needs excessive memory requirements and heavy computational complexity, implementation of turbo decoder on SDR system brings about many severe difficulties in practice. Especially, a turbo decoder requires very long processing time due to the fact that two MAP decoders inside the turbo decoder should exchange received data to be decoded from one to the other in order to resolve errors in the received signals. The proposed parallelization algorithm tremendously reduces the decoding time caused by the pair of MAP decoders. After analyzing the performance of the proposed parallelization algorithm, we implemented the parallelized turbo decoder on a GPU, which itself is a high-speed parallel processor. From experimental results obtained from implemented turbo decoder on both Xilinx Virtex-5 XC5VSX35 and TI TMS320TCI6488 TCP2(Turbo-DecoderCoprocessor2), we have verified that the throughput rate is remarkably increased by the proposed parallelization procedure.