Multi-Vdd를 위한 저전력 고성능 CMOS Level-up 시프터 설계

Abstract

In VLSI systems, one of the effective techniques to reduce power consumption is multi-Vdd design. Level shifters, which adjust the difference of Vdd input of each module, are essential in multi-Vdd systems. There are two kinds of level shifters called a level-up shifter and a level-down shifter. Especially, the level-up shifter is more complicate than the level-down shifter and the structure of level-up shifters determines its speed and delay. Hence there are many studies in designing of the level-up shifter. We propose a new level-up shifter design, which is faster and consumes less power than a conventional level-up shifter. A proposed level-up shifter has an upturned structure of the conventional design. This design is advantageous to reduce propagation delay, but the static leakage power may increase. To solve this problem, two additional NMOS transistors are cascaded to reduce the static leakage power consumption utilizing stacking effect. We compared delay and power consumption of the proposed design with those of the conventional design using HSPICE with a 45nm CMOS process. The results of our experiments showed that the proposed design reduced the delay by 9.9% and the power consumption by 20% compared with the conventional design, which means the proposed level-up shifter is more effective for multi-Vdd systems in terms of speed and power consumption than the conventional level-up shifter.