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다중화된 곱셈기를 이용한 델타-시그마 AD 컨버터용 디지털 데시메이션 필터
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 인병화 | - |
| dc.contributor.author | 박상규 | - |
| dc.date.accessioned | 2022-07-16T14:46:17Z | - |
| dc.date.available | 2022-07-16T14:46:17Z | - |
| dc.date.created | 2021-05-13 | - |
| dc.date.issued | 2012-06 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/165246 | - |
| dc.description.abstract | A hardware-effective digital decimation filter implementation used in a 16-bit delta-sigma A/D converter for audio application is described. The digital decimation filter uses multi-stage multi-rate signal processing to relax the filter design. Since the multipliers are the most hardware consuming components in digital filters, we optimized multiplier usage. This implementation is well suited for VLSI and can be applied to many other high resolution delta-sigma ADC. | - |
| dc.language | 한국어 | - |
| dc.language.iso | ko | - |
| dc.publisher | 대한전자공학회 | - |
| dc.title | 다중화된 곱셈기를 이용한 델타-시그마 AD 컨버터용 디지털 데시메이션 필터 | - |
| dc.title.alternative | Digital Decimation Filter for Delta-Sigma A/D Converter using Multiplexed Multiplier | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | 박상규 | - |
| dc.identifier.bibliographicCitation | 2012 대한전자공학회 하계학술대회, no. , pp. 33 - 35 | - |
| dc.relation.isPartOf | 2012 대한전자공학회 하계학술대회 | - |
| dc.citation.title | 2012 대한전자공학회 하계학술대회 | - |
| dc.citation.startPage | 33 | - |
| dc.citation.endPage | 35 | - |
| dc.type.rims | ART | - |
| dc.type.docType | Proceeding | - |
| dc.description.journalClass | 2 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | other | - |
| dc.identifier.url | http://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE02274928 | - |
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Collections - 서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles
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Related Researcher
- Park, Sang Gyu
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)