Detailed Information
Cited 0 time in 
Cited 0 time in 
Cited 0 time in
Metadata Downloads
다중화된 곱셈기를 이용한 델타-시그마 AD 컨버터용 디지털 데시메이션 필터Digital Decimation Filter for Delta-Sigma A/D Converter using Multiplexed Multiplier
- Other Titles
- Digital Decimation Filter for Delta-Sigma A/D Converter using Multiplexed Multiplier
- Issue Date
- Jun-2012
- Publisher
- 대한전자공학회
- Citation
- 2012 대한전자공학회 하계학술대회, no. , pp. 33 - 35
- Indexed
- OTHER
- Journal Title
- 2012 대한전자공학회 하계학술대회
- Start Page
- 33
- End Page
- 35
- Abstract
- A hardware-effective digital decimation filter implementation used in a 16-bit delta-sigma A/D converter for audio application is described. The digital decimation filter uses multi-stage multi-rate signal processing to relax the filter design. Since the multipliers are the most hardware consuming components in digital filters, we optimized multiplier usage. This implementation is well suited for VLSI and can be applied to many other high resolution delta-sigma ADC.
- Files in This Item
- Go to Link
- Appears in
Collections - 서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
Related Researcher
- Park, Sang Gyu
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)