A test method for power management of SoC-based microprocessors
DC Field | Value | Language |
---|---|---|
dc.contributor.author | You, Daecheol | - |
dc.contributor.author | Hwang, Young-Si | - |
dc.contributor.author | Ahn, Youngho | - |
dc.contributor.author | Chung, Ki-Seok | - |
dc.date.accessioned | 2022-07-16T18:06:21Z | - |
dc.date.available | 2022-07-16T18:06:21Z | - |
dc.date.created | 2021-05-11 | - |
dc.date.issued | 2011-12 | - |
dc.identifier.issn | 1550-4093 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/167022 | - |
dc.description.abstract | Power management in system-on-chip (SoC) has become one of the most crucial techniques for mobile devices. Among many intellectual properties (IP) of SoC, a microprocessor, which is one of the major power consumers in the system, is a key component in SoC power management. Controlling idle states for microprocessors, which is typically implemented by combinations of clock gating and power gating, needs a testing method at operating system level after pre-silicon verification. When a microprocessor performs power state transitions, the microprocessor's architectural state and the contents of local cache memory are corrupted. It cannot handle service requests from other peripheral IPs as well. Therefore, it is important to ensure that the system operates correctly with its original execution state after power state transitions. This paper addresses a testing methodology for power state switching of microprocessor at system level. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | A test method for power management of SoC-based microprocessors | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Chung, Ki-Seok | - |
dc.identifier.doi | 10.1109/MTV.2011.14 | - |
dc.identifier.scopusid | 2-s2.0-84857816318 | - |
dc.identifier.bibliographicCitation | Proceedings - International Workshop on Microprocessor Test and Verification, pp.28 - 31 | - |
dc.relation.isPartOf | Proceedings - International Workshop on Microprocessor Test and Verification | - |
dc.citation.title | Proceedings - International Workshop on Microprocessor Test and Verification | - |
dc.citation.startPage | 28 | - |
dc.citation.endPage | 31 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | Cache memory | - |
dc.subject.keywordPlus | Leakage currents | - |
dc.subject.keywordPlus | Microprocessor chips | - |
dc.subject.keywordPlus | Power management | - |
dc.subject.keywordPlus | Programmable logic controllers | - |
dc.subject.keywordPlus | Testing | - |
dc.subject.keywordPlus | Power consumers | - |
dc.subject.keywordPlus | Power gatings | - |
dc.subject.keywordPlus | Service requests | - |
dc.subject.keywordPlus | State-Retention | - |
dc.subject.keywordPlus | System levels | - |
dc.subject.keywordPlus | System on chips (SoC) | - |
dc.subject.keywordPlus | Testing method | - |
dc.subject.keywordPlus | Testing methodology | - |
dc.subject.keywordPlus | System-on-chip | - |
dc.subject.keywordAuthor | Microprocessor | - |
dc.subject.keywordAuthor | Power gating | - |
dc.subject.keywordAuthor | Power management test | - |
dc.subject.keywordAuthor | SoC | - |
dc.subject.keywordAuthor | State retention | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/6142328 | - |
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