Parallel LDPC decoding using CUDA and OpenMP
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Joo-Yul | - |
dc.contributor.author | Chung, Ki-Seok | - |
dc.date.accessioned | 2022-07-16T18:19:36Z | - |
dc.date.available | 2022-07-16T18:19:36Z | - |
dc.date.created | 2021-05-12 | - |
dc.date.issued | 2011-11 | - |
dc.identifier.issn | 1687-1472 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/167202 | - |
dc.description.abstract | Digital mobile communication technologies, such as next generation mobile communication and mobile TV, are rapidly advancing. Hardware designs to provide baseband processing of new protocol standards are being actively attempted, because of concurrently emerging multiple standards and diverse needs on device functions, hardware-only implementation may have reached a limit. To overcome this challenge, digital communication system designs are adopting software solutions that use central processing units or graphics processing units (GPUs) to implement communication protocols. In this article we propose a parallel software implementation of low density parity check decoding algorithms, and we use a multi-core processor and a GPU to achieve both flexibility and high performance. Specifically, we use OpenMP for parallelizing software on a multi-core processor and Compute Unified Device Architecture (CUDA) for parallel software running on a GPU. We process information on H-matrices using OpenMP pragmas on a multi-core processor and execute decoding algorithms in parallel using CUDA on a GPU. We evaluated the performance of the proposed implementation with respect to two different code rates for the China Multimedia Mobile Broadcasting (CMMB) standard, and we verified that the proposed implementation satisfies the CMMB bandwidth requirement. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | SPRINGER INTERNATIONAL PUBLISHING AG | - |
dc.title | Parallel LDPC decoding using CUDA and OpenMP | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Chung, Ki-Seok | - |
dc.identifier.doi | 10.1186/1687-1499-2011-172 | - |
dc.identifier.scopusid | 2-s2.0-84964456724 | - |
dc.identifier.wosid | 000301077300002 | - |
dc.identifier.bibliographicCitation | EURASIP JOURNAL ON WIRELESS COMMUNICATIONS AND NETWORKING, pp.1 - 8 | - |
dc.relation.isPartOf | EURASIP JOURNAL ON WIRELESS COMMUNICATIONS AND NETWORKING | - |
dc.citation.title | EURASIP JOURNAL ON WIRELESS COMMUNICATIONS AND NETWORKING | - |
dc.citation.startPage | 1 | - |
dc.citation.endPage | 8 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Telecommunications | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Telecommunications | - |
dc.subject.keywordPlus | PARITY-CHECK CODES | - |
dc.subject.keywordPlus | MULTI-CORE | - |
dc.subject.keywordPlus | SHANNON LIMIT | - |
dc.subject.keywordAuthor | LDPC | - |
dc.subject.keywordAuthor | decoder | - |
dc.subject.keywordAuthor | parallel processing | - |
dc.subject.keywordAuthor | CUDA | - |
dc.subject.keywordAuthor | graphic processing unit | - |
dc.identifier.url | https://jwcn-eurasipjournals.springeropen.com/articles/10.1186/1687-1499-2011-172 | - |
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