Enhancement of the device characteristics for nanoscale charge trap flash memory devices utilizing a metal spacer layer
DC Field | Value | Language |
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dc.contributor.author | Kim, Hyun Woo | - |
dc.contributor.author | You, Joo Hyung | - |
dc.contributor.author | Lee, Dea Uk | - |
dc.contributor.author | Kim, Tae Whan | - |
dc.contributor.author | Lee, Keun Woo | - |
dc.date.accessioned | 2022-07-16T19:17:54Z | - |
dc.date.available | 2022-07-16T19:17:54Z | - |
dc.date.created | 2021-05-11 | - |
dc.date.issued | 2011-09 | - |
dc.identifier.issn | 0000-0000 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/167725 | - |
dc.description.abstract | Nanoscale charge trap flash (CTF) memory devices with a metal spacer layer were designed to decrease the interference effect and to increase the fringing field effect and the coupling ratio. The optimum metal spacer depth of the memory devices was determined to enhance the device performance of the memory devices. The drain current and the threshold voltage shifts of the CTF memory devices were increased due to an increase in the fringing field and the coupling ratio resulting from the existence of the optimized metal spacer. The interference effect between neighboring cells was decreased due to the shielding of the electric field resulting from the existence of the metal spacer layer. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.title | Enhancement of the device characteristics for nanoscale charge trap flash memory devices utilizing a metal spacer layer | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Tae Whan | - |
dc.identifier.doi | 10.1109/SISPAD.2011.6035086 | - |
dc.identifier.scopusid | 2-s2.0-80055014581 | - |
dc.identifier.bibliographicCitation | International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, pp.203 - 206 | - |
dc.relation.isPartOf | International Conference on Simulation of Semiconductor Processes and Devices, SISPAD | - |
dc.citation.title | International Conference on Simulation of Semiconductor Processes and Devices, SISPAD | - |
dc.citation.startPage | 203 | - |
dc.citation.endPage | 206 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | Charge trap flash memories | - |
dc.subject.keywordPlus | coupling ratio | - |
dc.subject.keywordPlus | Coupling ratios | - |
dc.subject.keywordPlus | Device characteristics | - |
dc.subject.keywordPlus | Device performance | - |
dc.subject.keywordPlus | Fringing field effects | - |
dc.subject.keywordPlus | Fringing fields | - |
dc.subject.keywordPlus | interference effect | - |
dc.subject.keywordPlus | Interference effects | - |
dc.subject.keywordPlus | Nano scale | - |
dc.subject.keywordPlus | Spacer layer | - |
dc.subject.keywordPlus | Threshold voltage shifts | - |
dc.subject.keywordPlus | Charge trapping | - |
dc.subject.keywordPlus | Drain current | - |
dc.subject.keywordPlus | Electric fields | - |
dc.subject.keywordPlus | Equipment | - |
dc.subject.keywordPlus | Flash memory | - |
dc.subject.keywordPlus | Metals | - |
dc.subject.keywordPlus | Nanostructured materials | - |
dc.subject.keywordPlus | Nanotechnology | - |
dc.subject.keywordPlus | Threshold voltage | - |
dc.subject.keywordPlus | Field effect semiconductor devices | - |
dc.subject.keywordAuthor | charge trap flash memory | - |
dc.subject.keywordAuthor | coupling ratio | - |
dc.subject.keywordAuthor | fringing field | - |
dc.subject.keywordAuthor | interference effect | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/6035086 | - |
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