Enhancement of the device characteristics for nanoscale charge trap flash memory devices utilizing a metal spacer layer

Abstract

Nanoscale charge trap flash (CTF) memory devices with a metal spacer layer were designed to decrease the interference effect and to increase the fringing field effect and the coupling ratio. The optimum metal spacer depth of the memory devices was determined to enhance the device performance of the memory devices. The drain current and the threshold voltage shifts of the CTF memory devices were increased due to an increase in the fringing field and the coupling ratio resulting from the existence of the optimized metal spacer. The interference effect between neighboring cells was decreased due to the shielding of the electric field resulting from the existence of the metal spacer layer.