Detection of Spatial Defect Patterns Generated in Semiconductor Fabrication Processes

Abstract

Spatial defect patterns generated during integrated circuit (IC) manufacturing processes contain information about potential problems in the processes. The detection of these defect patterns is crucial to improve yield and reliability in IC manufacturing. This paper proposes a multistep defect analysis approach that provides clustering results with different levels of accuracy. A defect denoising step, based on the Kth nearest-neighbor noise removal technique, determines the existence of any clustered local defects on a wafer. If local defects exist, the denoising step separates local defects from global defects. A defect clustering step applies a similarity-based clustering technique to group the local defects into clusters according to their spatial locations. A pattern identification step identifies the pattern for each of the local defect clusters (i.e., linear, curvilinear, amorphous, or ring-shaped patterns) via various model selection criteria. Finally, a fine tuning step is applied in order to improve the accuracy of the clustering performance. The fine tuning step is based on model-based clustering with a fixed number of clusters and known patterns for each cluster. The results of both simulated and real wafer map data demonstrate the potential of our approach, both in terms of computational speed and detection accuracy, for analyzing general defect patterns generated during the IC fabrication process.