A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator
DC Field | Value | Language |
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dc.contributor.author | Park, Jea-Gun | - |
dc.contributor.author | Kim, Seong-Je | - |
dc.contributor.author | Shin, Mi-Hee | - |
dc.contributor.author | Song, Seung-Hyun | - |
dc.contributor.author | Chung, Sung-Woong | - |
dc.contributor.author | Enomoto, Hirofumi | - |
dc.contributor.author | Shim, Tae-Hun | - |
dc.date.accessioned | 2022-07-16T19:41:21Z | - |
dc.date.available | 2022-07-16T19:41:21Z | - |
dc.date.created | 2021-05-12 | - |
dc.date.issued | 2011-08 | - |
dc.identifier.issn | 0957-4484 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/167891 | - |
dc.description.abstract | A multi-level capacitor-less memory cell was fabricated with a fully depleted n-metal-oxide-semiconductor field-effect transistor on a nano-scale strained silicon channel on insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the silicon channel of the FD sSOI n-MOSFET enhanced the effective electron mobility to similar to 1.7 times that with an unstrained silicon channel. This thereby enables both front-and back-gate cell operations, demonstrating eight-level volatile memory-cell operation with a 1 ms retention time and 12 mu A memory margin. This is a step toward achieving a terabit volatile memory cell. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IOP PUBLISHING LTD | - |
dc.title | A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Jea-Gun | - |
dc.identifier.doi | 10.1088/0957-4484/22/31/315201 | - |
dc.identifier.scopusid | 2-s2.0-79960792706 | - |
dc.identifier.wosid | 000292689600003 | - |
dc.identifier.bibliographicCitation | NANOTECHNOLOGY, v.22, no.31, pp.1 - 7 | - |
dc.relation.isPartOf | NANOTECHNOLOGY | - |
dc.citation.title | NANOTECHNOLOGY | - |
dc.citation.volume | 22 | - |
dc.citation.number | 31 | - |
dc.citation.startPage | 1 | - |
dc.citation.endPage | 7 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Nanoscience & Nanotechnology | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | ELECTRON-TRANSPORT | - |
dc.subject.keywordPlus | SI MOSFETS | - |
dc.subject.keywordPlus | THICKNESS | - |
dc.subject.keywordPlus | LAYERS | - |
dc.identifier.url | https://iopscience.iop.org/article/10.1088/0957-4484/22/31/315201 | - |
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