ANALYSIS OF GROUND LAYOUT EFFECT IN CMOS CONCURRENT DUAL-BAND LNA

Abstract

Ground planes are often used on the integrated circuits. An improperly designed ground plane can be a major source of noise and attenuation to affect the circuit performances. Using a full-wave simulator HFSS, this article analyzes a ground plane effect in layout of a CMOS concurrent dual-band low-noise amplifier (LNA). The concurrent dual-band LNA that operates at 2.4 and 5.2 GHz is fabricated using 180-nm CMOS technology. Comparing with the circuit simulation result, the measured result shows a 7-dB gain reduction at 5.2 GHz. In an attempt to find the cause and solve the problem, a full-wave simulation that can analyze the layout effects is carried out. On the basis of the full-wave analysis, we determine that the ground plane potentially produces a parasitic inductive component which deteriorates the gain performance at the higher operating frequency band. A modified ground plane layout for reducing the parasitic inductance is proposed, and the LNA achieves the improved gain and noise performances similar to the circuit simulation.