Variations in the Memory Capability of Nonvolatile Memory Devices Fabricated Using Hybrid Composites of InP Nanoparticles and a Polystyrene Layer Due to the Scale-Down

Abstract

InP nanoparticles were formed using a solution method, and the InP nanoparticles that were embedded in a polystyrene (PS) layer were formed using the spin-coating method. The transmission electron microscopy images showed that the InP nanoparticles were randomly distributed in the PS layer. The measured capacitance voltage (C-V) of the Al/InP nanoparticles embedded in the PS layer/PS/p-Si(100) device at 300 K showed a clockwise hysteresis of the C-V curve. Based on the C-V results, the origin of variations in the memory storage of nonvolatile memory devices that were fabricated using InP nanoparticles embedded in a PS layer due to the scale-down was described.