Variations in the Memory Capability of Nonvolatile Memory Devices Fabricated Using Hybrid Composites of InP Nanoparticles and a Polystyrene Layer Due to the Scale-Down
- Authors
- Lee, SH; Yun, DY; Jung, JH; You, JH; Kim, TW; Ryu, E; Kim, SW
- Issue Date
- Jan-2011
- Publisher
- AMER SCIENTIFIC PUBLISHERS
- Keywords
- Nonvolatile Memory Devices; Polystyrene; InP Nanoparticles; Solution Method; Scale-Down
- Citation
- JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v.11, no.1, pp.449 - 452
- Indexed
- SCIE
SCOPUS
- Journal Title
- JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY
- Volume
- 11
- Number
- 1
- Start Page
- 449
- End Page
- 452
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/169247
- DOI
- 10.1166/jnn.2011.3172
- ISSN
- 1533-4880
- Abstract
- InP nanoparticles were formed using a solution method, and the InP nanoparticles that were embedded in a polystyrene (PS) layer were formed using the spin-coating method. The transmission electron microscopy images showed that the InP nanoparticles were randomly distributed in the PS layer. The measured capacitance voltage (C-V) of the Al/InP nanoparticles embedded in the PS layer/PS/p-Si(100) device at 300 K showed a clockwise hysteresis of the C-V curve. Based on the C-V results, the origin of variations in the memory storage of nonvolatile memory devices that were fabricated using InP nanoparticles embedded in a PS layer due to the scale-down was described.
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