Analysis and optimization of a resistive-feedback inverter LNA

Abstract

This article presents a new transistor size rule for a resistive-feedback inverter implemented as a low-noise amplifier (LNA) for wideband applications. To enhance the noise figure (NF) and voltage gain (A(v)), the inverter LNA requires large transconductance (G(m)), resulting in large current consumption (I-D). The proposed large-NMOS inverter-LNA obtains a better power efficiency (G(m)/I-D) with a smaller transistor compared with the conventional large-PMOS structure. Because there are trade-off relationships between NF, A(v), 3-dB bandwidth, and power dissipation in the inverter-LNA design, a figure-of-merit (FOM) including all of these parameters is maximized by varying the transistor size obtained from the graphical optimization. Thus, the proposed new size ratio rule achieves superior LNA performances compared to the conventional rule, as demonstrated by the theoretical analysis, simulation, optimization, and measurement. Measurements show a maximum power gain of 16.8 dB, a minimum NF of 1.84 dB, and a maximum third-order input intercept point of -9.4 dBm over 0.05 to 1.4 GHz while the LNA consumes 9.6 mW from a 1.5 V supply. The proposed LNA is implemented using a Samsung 65-nm RF CMOS process.