Retention Time Analysis in a 1T-DRAM With a Vertical Twin Gate and p(+)/i/n(+) Silicon Nanowire
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jang, Sung Hwan | - |
dc.contributor.author | Kim, Tae Whan | - |
dc.date.accessioned | 2022-09-19T11:32:22Z | - |
dc.date.available | 2022-09-19T11:32:22Z | - |
dc.date.created | 2022-09-08 | - |
dc.date.issued | 2022-09 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/171453 | - |
dc.description.abstract | In this work, we demonstrate a one-transistor, dynamic random access memory (1T-DRAM) with a very high retention time (RT), vertical twin gates, and a p(+)/i/n(+) nanowire via well-calibrated TCAD simulations. The 4F(2)-like cell array of the proposed 1T-DRAM can be achieved by realizing twin gates vertically. This 1T-DRAM has a high read current ratio (10(6) at 25 degrees C and 1-ns read duration) of state "1" to state "0," and, even when a severe word line (WL) and bitline (BL) disturbance is considered, exhibits a RT of similar to 3 s at 25 degrees C. The long RT, considering a severeWL/BL disturbance, increases the refresh interval time. A systematic analysis shows that the gate length can be scaled down to 10 nm with an acceptable RT (similar to 3 s) to make the fabrication easier by lowering the height of the silicon nanowire. Based on these results, we believe that our proposed 1T-DRAM will be a strong candidate for future DRAM devices. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Retention Time Analysis in a 1T-DRAM With a Vertical Twin Gate and p(+)/i/n(+) Silicon Nanowire | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Tae Whan | - |
dc.identifier.doi | 10.1109/TED.2022.3193349 | - |
dc.identifier.scopusid | 2-s2.0-85135745179 | - |
dc.identifier.wosid | 000833045100001 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.69, no.9, pp.4909 - 4913 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.citation.title | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.citation.volume | 69 | - |
dc.citation.number | 9 | - |
dc.citation.startPage | 4909 | - |
dc.citation.endPage | 4913 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | 1T DRAM CELL | - |
dc.subject.keywordPlus | MOSFET | - |
dc.subject.keywordAuthor | 4F(2) cell array | - |
dc.subject.keywordAuthor | bitline (BL) | - |
dc.subject.keywordAuthor | disturbance | - |
dc.subject.keywordAuthor | retention time (RT) | - |
dc.subject.keywordAuthor | single transistor dynamic random access memory (1T-DRAM) | - |
dc.subject.keywordAuthor | word line (WL) | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/9842372/ | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
222, Wangsimni-ro, Seongdong-gu, Seoul, 04763, Korea+82-2-2220-1365
COPYRIGHT © 2021 HANYANG UNIVERSITY.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.