Retention Time Analysis in a 1T-DRAM With a Vertical Twin Gate and p(+)/i/n(+) Silicon Nanowire
- Authors
- Jang, Sung Hwan; Kim, Tae Whan
- Issue Date
- Sep-2022
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- 4F(2) cell array; bitline (BL); disturbance; retention time (RT); single transistor dynamic random access memory (1T-DRAM); word line (WL)
- Citation
- IEEE TRANSACTIONS ON ELECTRON DEVICES, v.69, no.9, pp.4909 - 4913
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON ELECTRON DEVICES
- Volume
- 69
- Number
- 9
- Start Page
- 4909
- End Page
- 4913
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/171453
- DOI
- 10.1109/TED.2022.3193349
- ISSN
- 0018-9383
- Abstract
- In this work, we demonstrate a one-transistor, dynamic random access memory (1T-DRAM) with a very high retention time (RT), vertical twin gates, and a p(+)/i/n(+) nanowire via well-calibrated TCAD simulations. The 4F(2)-like cell array of the proposed 1T-DRAM can be achieved by realizing twin gates vertically. This 1T-DRAM has a high read current ratio (10(6) at 25 degrees C and 1-ns read duration) of state "1" to state "0," and, even when a severe word line (WL) and bitline (BL) disturbance is considered, exhibits a RT of similar to 3 s at 25 degrees C. The long RT, considering a severeWL/BL disturbance, increases the refresh interval time. A systematic analysis shows that the gate length can be scaled down to 10 nm with an acceptable RT (similar to 3 s) to make the fabrication easier by lowering the height of the silicon nanowire. Based on these results, we believe that our proposed 1T-DRAM will be a strong candidate for future DRAM devices.
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