A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Wang, Zhongkai | - |
dc.contributor.author | Choi, Minsoo | - |
dc.contributor.author | Kwon, Paul | - |
dc.contributor.author | Lee, Kyoungtae | - |
dc.contributor.author | Yin, Bozhi | - |
dc.contributor.author | Liu, Zhaokai | - |
dc.contributor.author | Park, Kwanseo | - |
dc.contributor.author | Biswas, Ayan | - |
dc.contributor.author | Han, Jaeduk | - |
dc.contributor.author | Du, Sijun | - |
dc.contributor.author | Alon, Elad | - |
dc.date.accessioned | 2022-09-19T13:39:55Z | - |
dc.date.available | 2022-09-19T13:39:55Z | - |
dc.date.created | 2022-09-08 | - |
dc.date.issued | 2022-06 | - |
dc.identifier.issn | 0743-1562 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/171598 | - |
dc.description.abstract | This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The prototype chip achieves 4.69 pJ/bit efficiency, 54mV eye height, 0.27UI eye width, and 97% RLM under -6dB channel loss at 50GHz. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Han, Jaeduk | - |
dc.identifier.doi | 10.1109/VLSITechnologyandCir46769.2022.9830237 | - |
dc.identifier.scopusid | 2-s2.0-85135213732 | - |
dc.identifier.bibliographicCitation | Digest of Technical Papers - Symposium on VLSI Technology, v.2022-June, pp.34 - 35 | - |
dc.relation.isPartOf | Digest of Technical Papers - Symposium on VLSI Technology | - |
dc.citation.title | Digest of Technical Papers - Symposium on VLSI Technology | - |
dc.citation.volume | 2022-June | - |
dc.citation.startPage | 34 | - |
dc.citation.endPage | 35 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | CMOS integrated circuits | - |
dc.subject.keywordPlus | Phase locked loops | - |
dc.subject.keywordPlus | Pulse amplitude modulation | - |
dc.subject.keywordPlus | Transmitters | - |
dc.subject.keywordPlus | 28nm | - |
dc.subject.keywordPlus | 28nm CMOS | - |
dc.subject.keywordPlus | CMOS | - |
dc.subject.keywordPlus | CMOS technology | - |
dc.subject.keywordPlus | Delta-sigma | - |
dc.subject.keywordPlus | Modulator clock | - |
dc.subject.keywordPlus | Serdes | - |
dc.subject.keywordPlus | Sub-sampling | - |
dc.subject.keywordPlus | Sub-sampling PLL | - |
dc.subject.keywordPlus | Timing control | - |
dc.subject.keywordAuthor | 28nm | - |
dc.subject.keywordAuthor | CMOS | - |
dc.subject.keywordAuthor | SerDes | - |
dc.subject.keywordAuthor | Sub-sampling PLL | - |
dc.subject.keywordAuthor | Transmitter | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/9830237 | - |
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