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Optimization of RunBefore decoder and first one detector for MPEG-4 AVC/H.264 CAVLC decoding

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dc.contributor.authorLee, S.-J.-
dc.contributor.authorPark, J.-Y.-
dc.contributor.authorChung, Ki Seok-
dc.date.accessioned2022-10-07T09:40:18Z-
dc.date.available2022-10-07T09:40:18Z-
dc.date.created2022-09-16-
dc.date.issued2008-12-
dc.identifier.issn0000-0000-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/171736-
dc.description.abstractIn this paper, we propose a novel RunBefore decoder and a new FOD (First One Detector) for MPEG-4 AVC/H.264 CAVLC decoding. By reusing common blocks aggressively, the proposed FOD has smaller area and less power consumption. Also a new RunBefore decoder which decodes two values in one clock has been designed to improve the decoding performance. The proposed CA VLC decoder has been designed in Verilog HDL, and synthesized by Synopsys' Design Compiler using MagnaChip 0.18μm CMOS cell library. Performance evaluation results show that our design has on average 48% faster than conventional designs.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-
dc.titleOptimization of RunBefore decoder and first one detector for MPEG-4 AVC/H.264 CAVLC decoding-
dc.typeArticle-
dc.contributor.affiliatedAuthorChung, Ki Seok-
dc.identifier.doi10.1109/ICED.2008.4786754-
dc.identifier.scopusid2-s2.0-63649117706-
dc.identifier.bibliographicCitation2008 International Conference on Electronic Design, ICED 2008, pp.1 - 5-
dc.relation.isPartOf2008 International Conference on Electronic Design, ICED 2008-
dc.citation.title2008 International Conference on Electronic Design, ICED 2008-
dc.citation.startPage1-
dc.citation.endPage5-
dc.type.rimsART-
dc.type.docTypeConference Paper-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscopus-
dc.subject.keywordPlusDesign-
dc.subject.keywordPlusMotion Picture Experts Group standards-
dc.subject.keywordPlusAVC/H.264-
dc.subject.keywordPlusCmos cell libraries-
dc.subject.keywordPlusConventional designs-
dc.subject.keywordPlusDecoding performance-
dc.subject.keywordPlusDesign compilers-
dc.subject.keywordPlusPerformance evaluations-
dc.subject.keywordPlusPower consumption-
dc.subject.keywordPlusSynopsys-
dc.subject.keywordPlusVerilog HDL-
dc.subject.keywordPlusDecoding-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/4786754-
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