Write buffer-aware address mapping for NAND flash memory devices
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Sungmin | - |
dc.contributor.author | Jung, Hoyoung | - |
dc.contributor.author | Shim, Hyoki | - |
dc.contributor.author | Kang, Sooyong | - |
dc.contributor.author | Cha, JaeHyuk | - |
dc.date.accessioned | 2022-10-07T10:01:41Z | - |
dc.date.available | 2022-10-07T10:01:41Z | - |
dc.date.created | 2022-09-16 | - |
dc.date.issued | 2008-09 | - |
dc.identifier.issn | 0000-0000 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/171849 | - |
dc.description.abstract | By using small-sized, next-generation NVRAM (such as MRAM, FeRAM and PRAM) as a write buffer, we can improve the overall performance of the NAND flash memorybased storage systems. However, traditional address mapping algorithms in Flash Translation Layer (FTL) software were designed without any consideration of the existence of write buffer. In this paper, we propose a novel write buffer-aware flash translation layer algorithm, optimistic FTL, which is designed to harmonize well with NVRAM write buffers. Simulation results show that the proposed optimistic FTL outperforms previous log block-based FTL algorithms. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.title | Write buffer-aware address mapping for NAND flash memory devices | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kang, Sooyong | - |
dc.contributor.affiliatedAuthor | Cha, JaeHyuk | - |
dc.identifier.doi | 10.1109/MASCOT.2008.4770592 | - |
dc.identifier.scopusid | 2-s2.0-65949122100 | - |
dc.identifier.bibliographicCitation | 2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS, pp.1 - 2 | - |
dc.relation.isPartOf | 2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS | - |
dc.citation.title | 2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS | - |
dc.citation.startPage | 1 | - |
dc.citation.endPage | 2 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | Flash translation layer | - |
dc.subject.keywordPlus | Mapping algorithms | - |
dc.subject.keywordPlus | NAND Flash | - |
dc.subject.keywordPlus | NAND flash memory | - |
dc.subject.keywordPlus | Simulation result | - |
dc.subject.keywordPlus | Storage systems | - |
dc.subject.keywordPlus | Buffer storage | - |
dc.subject.keywordPlus | Computer networks | - |
dc.subject.keywordPlus | Conformal mapping | - |
dc.subject.keywordPlus | Random access storage | - |
dc.subject.keywordPlus | Flash memory | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/4770592 | - |
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